Paper
Paper
388 entities#
1 Understanding UVM Coverage for RISC-V Processor Designs
6 2 Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing
6 3 Guiding Greybox Fuzzing with Mutation Testing
6 4 An Advanced Constrained Random Verification Environment for SystemC
6 5 Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator
5 6 ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers
5 7 Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM
5 8 Towards specification and testing of RISC-V ISA compliance
5 9 ReFuzz: Reusing Tests for Processor Fuzzing with Contextual Bandits
5 10 GoldenFuzz: Generative Golden Reference Hardware Fuzzing
5 11 RFuzz Paper
5 12 ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance
5 13 Genesys: Automatically Generating Representative Training Sets for Predictive Benchmarking
5 14 A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture
5 15 MicroTESK: An Extendable Framework for Test Program Generation
5 16 Constraint-based Random Stimuli Generation for Hardware Verification
5 17 Bug hunting SoC designs to achieve full functional coverage closure
5 18 Synthesizing Programs with Continuous Optimization
5 19 Multi-target Coverage-based Greybox Fuzzing (Master's Thesis 2025)
5 20 Test Program Generation for Functional Verification of PowerPC Processors in IBM
5 21 Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV
5 22 Paleari et al. 2010 x86 decoder differential testing
5 23 Pothineni et al. Maximal Convex Subgraph Enumeration
5 24 Li et al. Search Tree Enumeration Algorithm
5 25 Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging
5 26 DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs
4 27 Threadmill: A Post-Silicon Exerciser for Multi-Threaded Processors
4 28 Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V
4 29 Coverage-driven Stimuli Generation (Yang et al., 2012)
4 30 Verification of a RISC-V system with multiple cores
4 31 Using a constraint satisfaction formulation and solution techniques for random test program generation
4 32 CRAVE: An Advanced Constrained Random Verification Environment for SystemC
4 33 RISCSmith: Finding RISC-V CPU Bugs via Rich Instruction Construction and On-the-fly Differential Analysis
4 34 Understanding the RISC-V Verification Ecosystem
4 35 Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior
4 36 Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
4 37 Coverage-Guided Pre-Silicon Fuzzing of Open-Source Processors based on Leakage Contracts
4 38 TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
4 39 INSTILLER: Towards Efficient and Realistic RTL Fuzzing
4 40 DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing
4 41 DiffTest-H: Toward Semantic-Aware Communication in Hardware-Accelerated Co-Simulation
4 42 Tyagi et al. 2022
4 43 ScaleRTL: scaling LLMs with reasoning data and test-time compute for accurate RTL code generation
4 44 StimulusRL: A Universal Deep Reinforcement Learning Stimulus Agent for Coverage-Driven Chip Design Verification
4 45 Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation
4 46 A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation
4 47 RISC-V Processor Verification Requires the Full Toolbox
4 48 AI-Assisted Proof Strategy Selection for RISC-V Formal Verification
3 49 Symbiotic Verification of RISC-V Processors
3 50 Open-Source RISC-V Vector Test Suites: A Comparative Analysis
3 51 RISC-V Processor Verification with Coverage-guided Aging
3 52 A UVM based Reusable Framework for End-To-End Verification of Power ISA Cores (IJISAE 2024)
3 53 UVM Verification of RISC-V Instruction Set (ICAECA 2024)
3 54 Automated Testing, Verification and Repair of RTL Hardware Designs (UCB EECS TR 2024-157)
3 55 RISC-V Formal: A Framework for Formal Specification and Verification of RISC-V ISA
3 56 TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities
3 57 HDFI
3 58 Using Constraint Satisfaction Formulations and Solution Techniques for Random Test Program Generation
3 59 Coverage directed test generation for functional verification using Bayesian networks
3 60 Instiller paper
3 61 Micro-processor verification using a C++11 sequence-based stimulus engine
3 62 Fuzzing Hardware Like Software
3 63 X-Gen: A Random Test-Case Generator for Systems and SoCs
3 64 A Test Generation Framework for Datapath Floating-Point Verification
3 65 MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors
3 66 An SPU Reference Model for Simulation, Random Test Generation and Verification
3 67 Wu et al. 2025 GoldenFuzz
3 68 PIM-DFI
3 69 Microprocessor Verification via Feedback-Adjusted Markov Models
3 70 Hybrid Automata and Formal Modeling for Safety-Critical RISC-V Control Systems
3 71 RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs
3 72 Benchmarking Large Language Models for Automated Verilog RTL Code Generation
3 73 Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
3 74 Adaptive Test Program Generation: Planning for the Unplanned
3 75 SiliFuzz: Fuzzing CPUs by Proxy
3 76 HeteroFuzz: Fuzz Testing to Detect Platform Dependent Divergence for Heterogeneous Applications
3 77 FuzzWiz - Fuzzing Framework for Efficient Hardware Coverage
3 78 Reconfigurable Model-Based Test Program Generator for Microprocessors
3 79 Constraint satisfaction for test program generation
3 80 Graph-Based Functional Test Program Generation for Pipelined Processors
2 81 Functional Test Generation using SAT-based Bounded Model Checking
2 82 Piparazzi: A Test Program Generator for Micro-architecture Flow Verification
2 83 AFL White-Paper
2 84 DiFuzzRTL Paper
2 85 SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels
2 86 DeepTrans - A Model-Based Approach to Functional Verification of Address Translation Mechanisms
2 87 DAPO: an open-source LLM reinforcement learning system at scale
2 88 A Hybrid Verification Solution to RISC-V Vector Extension (C. Li et al.)
2 89 Testbench Flexibility as a Foundation for Success (A.S. Carretero et al.)
2 90 Addressing Verification Challenges of Heterogeneous Systems Based on IBM Power9
2 91 Universal fuzzing via large language models
2 92 BugGen: a self-correcting multi-agent LLM pipeline for realistic RTL bug synthesis
2 93 Comprehensive Verilog Design Problems (CVDP) benchmark
2 94 Decomposed prompting: a modular approach for solving complex tasks
2 95 Model Based Test Generation for Processor Verification
2 96 Advanced Verification Suite for RISC-V Cores
2 97 FloppyFloat: An open source floating point library for instruction set simulators
2 98 RISC-V VP++: Next generation open-source virtual prototype
2 99 Specification-Driven Directed Test Generation for Validation of Pipelined Processors
2 100 HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
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