Paper
Paper
280 entities#
1 DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing
4 2 INSTILLER: Towards Efficient and Realistic RTL Fuzzing
4 3 StimulusRL: A Universal Deep Reinforcement Learning Stimulus Agent for Coverage-Driven Chip Design Verification
4 4 Threadmill: A Post-Silicon Exerciser for Multi-Threaded Processors
4 5 TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
4 6 Coverage-Guided Pre-Silicon Fuzzing of Open-Source Processors based on Leakage Contracts
4 7 HDFI
3 8 Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
3 9 FuzzWiz - Fuzzing Framework for Efficient Hardware Coverage
3 10 X-Gen: A Random Test-Case Generator for Systems and SoCs
3 11 A Test Generation Framework for Datapath Floating-Point Verification
3 12 Using Constraint Satisfaction Formulations and Solution Techniques for Random Test Program Generation
3 13 Adaptive Test Program Generation: Planning for the Unplanned
3 14 Instiller paper
3 15 PIM-DFI
3 16 Fuzzing Hardware Like Software
3 17 Closing the RISC-V compliance gap: Looking from the negative testing side
3 18 Benchmarking Large Language Models for Automated Verilog RTL Code Generation
3 19 RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs
3 20 MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors
3 21 SiliFuzz: Fuzzing CPUs by Proxy
3 22 TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities
3 23 Micro-processor verification using a C++11 sequence-based stimulus engine
3 24 Coverage directed test generation for functional verification using Bayesian networks
3 25 Microprocessor Verification via Feedback-Adjusted Markov Models
3 26 RISC-V Formal: A Framework for Formal Specification and Verification of RISC-V ISA
3 27 Symbiotic Verification of RISC-V Processors
3 28 AI-Assisted Proof Strategy Selection for RISC-V Formal Verification
3 29 Hybrid Automata and Formal Modeling for Safety-Critical RISC-V Control Systems
3 30 Wu et al. 2025 GoldenFuzz
3 31 HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
2 32 Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
2 33 Testbench Flexibility as a Foundation for Success (A.S. Carretero et al.)
2 34 Functional Test Generation using SAT-based Bounded Model Checking
2 35 Using a constraint satisfaction formulation and solution techniques for random test program generation
2 36 Graph-Based Functional Test Program Generation for Pipelined Processors
2 37 StarCoder 2 and The Stack v2: The Next Generation
2 38 HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
2 39 AFL White-Paper
2 40 Automatic generation of test inputs for Mercury
2 41 seL4: Formal Verification of an OS Kernel
2 42 Extensible and configurable RISC-V based virtual prototype
2 43 CV32E40P updates: customizing an open-source RISC-V core at industrial-grade
2 44 RFUZZ: Coverage-directed fuzz testing of RTL on FPGAs
2 45 Handcrafted Inversions Made Operational on Operational Semantics
2 46 The TaPaSCo Open-Source Toolflow
2 47 RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
2 48 TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
2 49 SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels
2 50 Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation
2 51 Assumption-based Pruning in Conditional CSP
2 52 Automatic Generation of Validation Stimuli for Application-Specific Processors
2 53 Industrial Experience with Test Generation Languages for Processor Verification
2 54 Advanced Verification Suite for RISC-V Cores
2 55 Functional Verification of the POWER5 Microprocessor and POWER5 Multiprocessor Systems
2 56 Automation and Optimization of Coverage-driven Verification
2 57 A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
2 58 Design and Verification of SystemC Transaction-Level Models
2 59 IBM Israel Technical Report 88.290
2 60 CORE-V Verification Strategy
2 61 FloppyFloat: An open source floating point library for instruction set simulators
2 62 R2V: A RISC-V to Verilog Translation Framework for Formal Verification
2 63 catnap: Generating Test Suites of Constrained Combinatorial Testing with Answer Set Programming
2 64 RISC-V Debug Specification
2 65 Crafting a Million Instructions/Sec RISCV-DV
2 66 RV-Match: A Formal RISC-V Instruction-Level Semantics Matcher
2 67 SMT-based Bounded Model Checking for RISC-V Control Logic
2 68 CSRFormal: Formal Verification of Control and Status Registers in RISC-V
2 69 TMDFI
2 70 RISC-V VP++: Next generation open-source virtual prototype
2 71 Comparative Evaluation of Open-Source Formal Tools for RISC-V Processor Verification
2 72 Scalability of Formal Verification in Multi-Core RISC-V Systems
2 73 Deep Inference of RTL Assertions Using Transformer Models
2 74 RISC-V Instruction Set Manual Volume I
2 75 Universal fuzzing via large language models
2 76 Addressing Verification Challenges of Heterogeneous Systems Based on IBM Power9
2 77 Constraint satisfaction for test program generation
2 78 MA2TG: A Functional Test Program Generator for Microprocessor Verification
2 79 Model Based Test Generation for Processor Verification
2 80 A Hybrid Verification Solution to RISC-V Vector Extension (C. Li et al.)
2 81 Reconfigurable Model-Based Test Program Generator for Microprocessors
2 82 Specification-Driven Directed Test Generation for Validation of Pipelined Processors
2 83 DiFuzzRTL Paper
2 84 DeepTrans - A Model-Based Approach to Functional Verification of Address Translation Mechanisms
2 85 Micro-Architecture Coverage Directed Generation of Test Programs
1 86 Proceedings Article 2025-10-26
1 87 Directing greybox fuzzing to discover bugs in hardware and software
1 88 Automated Synthesis of Symbolic Instruction Encodings from I/O Samples (godefroid:pldi:2012)
1 89 Comprehensive RISC-V floating-point verification: Efficient coverage models and constraint-based test generation
1 90 Hybrid Intelligent Testing in Simulation-Based Verification
1 91 Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic
1 92 A Complete Formal Semantics of x86-64 User-Level ISA (dasgupta:pldi)
1 93 User Defined Coverage—A Tool Supported Methodology for Design Verification
1 94 Model-Based Test Generation For Processor Design Verification
1 95 Optimizing Design Verification using Machine Learning: Doing better than Random
1 96 Adaptive Test Program Generation (US 2003/0130813 A1)
1 97 Writing Testbenches: Functional Verification of HDL Models
1 98 Nuts and Bolts of Core and SoC Verification
1 99 Hole analysis for functional coverage data
1 100 Microprocessor design verification by two-phase evolution of variable length tests
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