Paper
Paper
376 entities#
1 GenHuzz: An Efficient Generative Hardware Fuzzer
6 2 EPEX: Processor Verification by Equivalent Program Execution
6 3 Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing
6 4 Understanding UVM Coverage for RISC-V Processor Designs
6 5 Synthesizing Programs with Continuous Optimization
5 6 Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV
5 7 ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers
5 8 A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture
5 9 MicroTESK: An Extendable Framework for Test Program Generation
5 10 Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM
5 11 Constraint-based Random Stimuli Generation for Hardware Verification
5 12 Bug hunting SoC designs to achieve full functional coverage closure
5 13 Multi-target Coverage-based Greybox Fuzzing (Master's Thesis 2025)
5 14 Test Program Generation for Functional Verification of PowerPC Processors in IBM
5 15 Towards specification and testing of RISC-V ISA compliance
5 16 Paleari et al. 2010 x86 decoder differential testing
5 17 Pothineni et al. Maximal Convex Subgraph Enumeration
5 18 Li et al. Search Tree Enumeration Algorithm
5 19 Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging
5 20 GoldenFuzz: Generative Golden Reference Hardware Fuzzing
5 21 RFuzz Paper
5 22 ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance
5 23 Genesys: Automatically Generating Representative Training Sets for Predictive Benchmarking
5 24 Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator
5 25 DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing
4 26 Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior
4 27 Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
4 28 StimulusRL: A Universal Deep Reinforcement Learning Stimulus Agent for Coverage-Driven Chip Design Verification
4 29 RISC-V Processor Verification Requires the Full Toolbox
4 30 Tyagi et al. 2022
4 31 ScaleRTL: scaling LLMs with reasoning data and test-time compute for accurate RTL code generation
4 32 INSTILLER: Towards Efficient and Realistic RTL Fuzzing
4 33 Threadmill: A Post-Silicon Exerciser for Multi-Threaded Processors
4 34 Coverage-Guided Pre-Silicon Fuzzing of Open-Source Processors based on Leakage Contracts
4 35 Understanding the RISC-V Verification Ecosystem
4 36 Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V
4 37 TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
4 38 CRAVE: An Advanced Constrained Random Verification Environment for SystemC
4 39 RISCSmith: Finding RISC-V CPU Bugs via Rich Instruction Construction and On-the-fly Differential Analysis
4 40 A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation
4 41 Verification of a RISC-V system with multiple cores
4 42 DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs
4 43 Using a constraint satisfaction formulation and solution techniques for random test program generation
4 44 DiffTest-H: Toward Semantic-Aware Communication in Hardware-Accelerated Co-Simulation
4 45 Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation
4 46 Coverage-driven Stimuli Generation (Yang et al., 2012)
4 47 X-Gen: A Random Test-Case Generator for Systems and SoCs
3 48 SiliFuzz: Fuzzing CPUs by Proxy
3 49 Symbiotic Verification of RISC-V Processors
3 50 A Test Generation Framework for Datapath Floating-Point Verification
3 51 Using Constraint Satisfaction Formulations and Solution Techniques for Random Test Program Generation
3 52 HDFI
3 53 MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors
3 54 An SPU Reference Model for Simulation, Random Test Generation and Verification
3 55 HeteroFuzz: Fuzz Testing to Detect Platform Dependent Divergence for Heterogeneous Applications
3 56 Hybrid Automata and Formal Modeling for Safety-Critical RISC-V Control Systems
3 57 RISC-V Formal: A Framework for Formal Specification and Verification of RISC-V ISA
3 58 Open-Source RISC-V Vector Test Suites: A Comparative Analysis
3 59 Micro-processor verification using a C++11 sequence-based stimulus engine
3 60 Fuzzing Hardware Like Software
3 61 PIM-DFI
3 62 FuzzWiz - Fuzzing Framework for Efficient Hardware Coverage
3 63 AI-Assisted Proof Strategy Selection for RISC-V Formal Verification
3 64 Instiller paper
3 65 Adaptive Test Program Generation: Planning for the Unplanned
3 66 Wu et al. 2025 GoldenFuzz
3 67 Constraint satisfaction for test program generation
3 68 RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs
3 69 Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
3 70 Coverage directed test generation for functional verification using Bayesian networks
3 71 Benchmarking Large Language Models for Automated Verilog RTL Code Generation
3 72 TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities
3 73 Reconfigurable Model-Based Test Program Generator for Microprocessors
3 74 Microprocessor Verification via Feedback-Adjusted Markov Models
3 75 RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
2 76 HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
2 77 Automatic generation of test inputs for Mercury
2 78 Addressing Verification Challenges of Heterogeneous Systems Based on IBM Power9
2 79 CV32E40P updates: customizing an open-source RISC-V core at industrial-grade
2 80 The TaPaSCo Open-Source Toolflow
2 81 Model-Based Test Generation For Processor Design Verification
2 82 SpecDoctor: Differential Fuzz Testing to Find Transient Execution Vulnerabilities
2 83 Automatic Generation of Validation Stimuli for Application-Specific Processors
2 84 Automation and Optimization of Coverage-driven Verification
2 85 A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
2 86 Design and Verification of SystemC Transaction-Level Models
2 87 IBM Israel Technical Report 88.290
2 88 R2V: A RISC-V to Verilog Translation Framework for Formal Verification
2 89 RV-Match: A Formal RISC-V Instruction-Level Semantics Matcher
2 90 SMT-based Bounded Model Checking for RISC-V Control Logic
2 91 CSRFormal: Formal Verification of Control and Status Registers in RISC-V
2 92 Comparative Evaluation of Open-Source Formal Tools for RISC-V Processor Verification
2 93 Scalability of Formal Verification in Multi-Core RISC-V Systems
2 94 Deep Inference of RTL Assertions Using Transformer Models
2 95 MA2TG: A Functional Test Program Generator for Microprocessor Verification
2 96 RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Hardware Fuzzing
2 97 Feedback-based Coverage Directed Test Generation: An industrial evaluation
2 98 RFUZZ: Coverage-directed fuzz testing of RTL on FPGAs
2 99 Extensible and configurable RISC-V based virtual prototype
2 100 Verma et al. Maximal Clique Enumeration for Custom Instructions
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