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Comprehensive Verilog Design Problems (CVDP) benchmark

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First seen 9/3/2026

Last seen 9/3/2026

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NEIGHBORHOOD

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graph · Comprehensive Verilog Design Problems (CVDP) benchmark · depth=1

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RELATIONSHIPS

1 connections

GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation ← mentions 100% 2e evidence

The paper uses CVDP benchmark for deriving fine-grained mutation operators.