Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Paper

First seen 8/7/2026

Last seen 8/7/2026

Evidence 4 chunks

NEIGHBORHOOD

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15 connections

FreeRTOS uses → 95% 2e

FreeRTOS is used as the software application for application-driven co-simulation.

Co-Simulation uses → 98% 2e

The paper employs co-simulation as one of its two core verification techniques for system-level verification.

The paper employs Coverage-Guided Fuzzing as one of its two core verification techniques.

The RISC-V PLIC is used as a case-study peripheral to evaluate the proposed methodology.

RISC-V VP uses → 97% 2e

RISC-V VP provides the TLM PLIC reference model used in the methodology.

Tracalyzer uses → 96% 1e

Tracalyzer is used to analyze execution traces of FreeRTOS for mismatch identification.

coverage metric evaluates → 95% 1e

The paper evaluates coverage metrics including line, function, and branch coverage for TLM and RTL peripherals.

Muhammad Hassan authored by → 97% 1e

Muhammad Hassan is listed as an author of the cross-level verification paper.

Rolf Drechsler authored by → 97% 1e

Rolf Drechsler is listed as an author of the cross-level verification paper.

Sallar Ahmadi-Pour authored by → 98% 1e

Sallar Ahmadi-Pour is listed as an author of the paper on synergistic verification.

University of Bremen published by → 90% 1e

The paper is produced by researchers at the University of Bremen.

Virtual Prototype uses → 97% 1e

The paper is driven by Virtual Prototype as the reference model foundation.

LLVM libFuzzer uses → 97% 1e

LLVM libFuzzer is employed as the fuzzer within the CGF testbench.

Verilator uses → 96% 1e

Verilator is used to compile the SpinalHDL RTL PLIC to SystemC RTL.

SpinalHDL uses → 96% 1e

SpinalHDL is used to generate the RTL PLIC description.