DeepTrans is a 2003 paper by Adir, Emek, Katz, and Koyfman on a model-based approach to functional verification of address translation mechanisms. The work is cited as appearing in the Fourth International Workshop on Microprocessor Test and Verification (MTV’03), pages 3–6. In later IBM hardware-verification context, DeepTrans is described as a specialized test generator for address translation that became part of Genesys PE.

No graph connections found for this entity yet. It may appear in future ingestion runs.