Overview

DeepTrans - A Model-Based Approach to Functional Verification of Address Translation Mechanisms is a paper cited as a 2003 publication by A. Adir, R. Emek, Y. Katz, and A. Koyfman. The cited venue is the Fourth International Workshop on Microprocessor Test and Verification (MTV’03), where it appears on pages 3–6.

Technical focus

The paper’s title identifies its subject as a model-based approach to the functional verification of address translation mechanisms. In the later IBM hardware-verification literature in which it is cited, DeepTrans is described as one of two specialized test generators developed after users requested new capabilities to make complex architectural mechanisms easier to verify. DeepTrans is specifically associated with the address translation area.

Relationship to Genesys PE

The cited IBM context states that new verification capabilities introduced by Genesys PE led users to request additional tool support for complex architectural mechanisms. This led to the development of specialized test generators including DeepTrans for address translation and FP-Gen for floating-point verification. The same source states that both tools became part of Genesys PE.

Bibliographic record from available evidence

Evidence limitations

The available evidence provides a bibliographic citation and later contextual description of DeepTrans within IBM’s verification-tool ecosystem. It does not provide the paper’s abstract, methodology details, experimental results, or implementation specifics beyond its characterization as model-based and focused on address translation verification.