Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV

Paper

First seen 8/1/2026

Last seen 8/1/2026

Evidence 5 chunks

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RELATIONSHIPS

24 connections

SMV model checker uses → 100% 3e

The paper applies SMV model checker to generate test programs

Model Checking uses → 100% 2e

The paper applies model checking to generate functional test programs

DLX processor evaluates → 100% 2e

The paper applies its methodology on a single-issue DLX processor as a case study

processor model uses → 100% 2e

The paper extracts and uses a processor model from the ADL specification

Counterexample Generation uses → 100% 2e

The paper uses counterexamples generated by SMV as functional test programs

Architecture Description Language uses → 100% 2e

The paper specifies processor architecture in an ADL to drive test generation

SAT-based Bounded Model Checking mentions → 90% 1e

The paper mentions investigating SAT-based bounded model checkers as future work

RTL description mentions → 90% 1e

The paper mentions applying tests on RTL description as future work

Simulation-Based Verification compares with → 90% 1e

The paper contrasts formal techniques with simulation-based approaches

SMV language uses → 100% 1e

Both the processor model and properties are described using the SMV language

feedback path uses → 90% 1e

The paper generates testcases that exercise feedback paths in the pipeline

Pipeline Path uses → 90% 1e

The paper uses pipeline paths as captured in the ADL to drive test generation

Data-transfer Path uses → 90% 1e

The paper uses data-transfer paths as captured in the ADL

read-after-write hazard mentions → 90% 1e

The paper shows a read-after-write hazard example that sets the stall bit

controllability problem mentions → 90% 1e

The paper identifies the controllability problem when assigning specific values to internal registers

PowerPC Processor mentions → 80% 1e

The paper mentions PowerPC processor in the context of related work

FSM-based processor modeling mentions → 80% 1e

The paper references FSM-based processor modeling in related work by Iwashita et al.

Prabhat Mishra authored by → 100% 1e

The paper is authored by Prabhat Mishra

Instruction Set Architecture mentions → 80% 1e

The paper references extraction of ISA model from implementation in related work

Nikil Dutt authored by → 100% 1e

The paper is authored by Nikil Dutt

Center for Embedded Computer Systems, University of California, Irvine published by → 100% 1e

The paper is published as a CECS technical report from UC Irvine

functional test program generation introduces → 100% 1e

The paper proposes a model checking based approach to automatically generate functional test programs for pipelined processors

EXPRESSION ADL uses → 100% 1e

The paper uses EXPRESSION ADL to specify the DLX architecture

cycle-accurate structural simulator uses → 100% 1e

The paper uses a cycle-accurate structural simulator to generate expected results for counterexamples