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Architecture Description Language

Concept

An Architecture Description Language (ADL) is a formal notation used to capture the architecture of a processor, system-on-chip, or other computational system so that downstream artifacts can be generated or driven from a single specification. Classical processor ADLs such as EXPRESSION ADL, nML, Sim-nML, and VADL enable automated generation of software toolkits (assemblers, compilers, linkers, simulators), synthesizable HDL/RTL reference models, design-space exploration, formal-verification property suites, and ADL-driven test-program generators (e.g., the MicroTESK framework, MA2TG, and Mishra–Dutt graph-based SMV-based generation). ADLs also extend to non-classical domains such as QADL for quantum software architecture.

First seen 5/26/2026
Last seen 8/1/2026
Evidence 23 chunks
Wiki v8

WIKI

Overview

An Architecture Description Language (ADL) is a language used to capture an architecture specification so that downstream design, simulation, compilation, exploration, or validation artifacts can be generated from it. In a language-driven design-space exploration flow for programmable embedded systems, the processor, coprocessor, and memory subsystem are captured using an ADL; the ADL specification is then used to generate a software toolkit including a compiler, simulator, and assembler, and to provide architectural-quality feedback to the designer. [C1]

In test-program-generation frameworks for microprocessors, an ADL serves as the input format for a translator that builds a design model and a coverage model of the microprocessor under test; test templates written in a separate template description language (TDL) then use those models to drive test-program generation. [C2]

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RELATIONSHIPS

15 connections
EXPRESSION ADL ← implements 100% 4e
EXPRESSION ADL is an implementation of the Architecture Description Language concept
MicroTESK ← uses 100% 4e
MicroTESK uses ADL descriptions to configure the test program generator for target microprocessors.
LISA ← implements 95% 4e
LISA is an ADL tool for automatic generation of simulators and compilers for processors.
EXPRESSION ← implements 90% 2e
EXPRESSION is a language for architecture exploration and serves as an ADL.
The paper specifies processor architecture in an ADL to drive test generation
ISDL ← implements 90% 1e
ISDL is an architecture description language for processor design.
MIMOLA ← implements 90% 1e
MIMOLA is an architecture description language for processor design.
LISA ADL ← implements 90% 1e
LISA is an architecture description language for processor design.
nML ← implements 90% 1e
nML is an architecture description language for processor design.
MA2TG ← uses 100% 1e
MA2TG uses ADL specification to simplify microprocessor architecture modeling.
functional test program generation ← uses 100% 1e
The test program generation is driven by an ADL specification
The paper mentions ADL-based approaches and their limitations compared to the proposed method.
Sim-nML ← implements 100% 1e
Sim-nML is an ADL supported by MicroTESK for instruction-level specifications.
Facile ← implements 80% 1e
Facile is an ADL-based tool for automatic generation of processor tools.
The paper mentions ADLs as related prior work

CITATIONS

7 sources
7 citations — click to expand
[1] ADL specifications are used to drive SMV-based functional test program generation, with the DLX processor used as the case study; the SMV description is generated automatically from the ADL specification using a library of generic architectural components. Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV
[2] The model-based approach to test program generation decomposes the problem into test templates (TTs), testing knowledge (TK), and an instruction-set model (ISM), summarized as TPs = TTs + TK + ISM. MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors
[3] MicroTESK uses ADLs (nML and Sim-nML) to specify microprocessors and configures subsystems not well suited to ADLs (MMU, PCU) via lightweight configuration files; TPs = AS + CFs. MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors
[4] EXPRESSION ADL captures the structure, behavior, and mapping of a processor; from an EXPRESSION ADL specification a synthesizable HDL/RTL description can be generated and used as a golden reference model for equivalence checking. MicroTESK: An Extendable Framework for
[5] MA2TG is an ADL-driven, constraint-solving-based functional test program generator for microprocessors, demonstrated on DLX, that can produce random test programs and instruction sequences satisfying a user constraints file. MA2TG: A Functional Test Program Generator for Microprocessor Verification
[6] VADL/OpenVADL is a processor description language with separated ISA and microarchitecture specifications that generates assemblers, compilers, linkers, simulators, HDL specifications, test cases, and documentation. The Vienna Architecture Description Language
[7] QADL is a Quantum Architecture Description Language prototype, inspired by classical ADLs, providing a graphical interface, parser, and Qiskit-integrated execution environment, evaluated on quantum teleportation and Grover's search. QADL: Prototype of Quantum Architecture Description Language