Paper
Paper
388 entities#
1 Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
2 2 StarCoder 2 and The Stack v2: The Next Generation
2 3 RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
2 4 ISA semantics for ARMv8-a, RISC-V, and CHERI-MIPS
2 5 A Complete Formal Semantics of x86-64 User-level Instruction Set Architecture
2 6 catnap: Generating Test Suites of Constrained Combinatorial Testing with Answer Set Programming
2 7 seL4: Formal Verification of an OS Kernel
2 8 Crafting a Million Instructions/Sec RISCV-DV
2 9 Handcrafted Inversions Made Operational on Operational Semantics
2 10 TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
2 11 HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
2 12 Automatic generation of test inputs for Mercury
2 13 CORE-V Verification Strategy
2 14 CV32E40P updates: customizing an open-source RISC-V core at industrial-grade
2 15 RISC-V Debug Specification
2 16 The TaPaSCo Open-Source Toolflow
2 17 RISC-V Instruction Set Manual Volume I
2 18 Model-Based Test Generation For Processor Design Verification
2 19 SpecDoctor: Differential Fuzz Testing to Find Transient Execution Vulnerabilities
2 20 Automatic Generation of Validation Stimuli for Application-Specific Processors
2 21 Extensible and configurable RISC-V based virtual prototype
2 22 RFUZZ: Coverage-directed fuzz testing of RTL on FPGAs
2 23 Automation and Optimization of Coverage-driven Verification
2 24 A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
2 25 Design and Verification of SystemC Transaction-Level Models
2 26 IBM Israel Technical Report 88.290
2 27 R2V: A RISC-V to Verilog Translation Framework for Formal Verification
2 28 RV-Match: A Formal RISC-V Instruction-Level Semantics Matcher
2 29 SMT-based Bounded Model Checking for RISC-V Control Logic
2 30 CSRFormal: Formal Verification of Control and Status Registers in RISC-V
2 31 Comparative Evaluation of Open-Source Formal Tools for RISC-V Processor Verification
2 32 Scalability of Formal Verification in Multi-Core RISC-V Systems
2 33 Deep Inference of RTL Assertions Using Transformer Models
2 34 Feedback-based Coverage Directed Test Generation: An industrial evaluation
2 35 TMDFI
2 36 Verma et al. Maximal Clique Enumeration for Custom Instructions
2 37 GoldenFuzz: A Novel Two-Stage Hardware Fuzzing Framework
2 38 RISC-V Manual
2 39 Towards Efficient and Automated Side Channel Evaluations at Design Time
2 40 A General Framework for Hindley/Milner Type Systems with Constraints
2 41 Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification
2 42 RVX-a tool for concolic testing of embedded binaries targeting RISC-V platforms
2 43 Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation
2 44 HW/SW Co-Verification using Bounded Model Checking (Große et al., 2006)
2 45 Automatic Constraint Generation for Guided Random Simulation (Yeh & Huang, 2010)
2 46 Assumption-based Pruning in Conditional CSP
2 47 Industrial Experience with Test Generation Languages for Processor Verification
2 48 Functional Verification of the POWER5 Microprocessor and POWER5 Multiprocessor Systems
2 49 MA2TG: A Functional Test Program Generator for Microprocessor Verification
2 50 RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Hardware Fuzzing
2 51 Between MDPs and Semi-MDPs: A Framework for Temporal Abstraction in Reinforcement Learning
1 52 Comprehensive RISC-V floating-point verification: Efficient coverage models and constraint-based test generation
1 53 CHIA arXiv paper (arXiv:2606.27350)
1 54 AVPGEN: Architecture Verification Program Generation for Processor Conformance Testing
1 55 Monadic Constraint Programming
1 56 A Language and Preprocessor for User-Controlled Generation of Synthetic Programs
1 57 Hybrid Intelligent Testing in Simulation-Based Verification
1 58 Instruction-Level Abstraction (ILA): A Uniform Specification for SoC Verification (huang:todaes:2019)
1 59 Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic
1 60 Unified hw/sw coverage: A novel metric to boost coverage-guided fuzzing for virtual prototype based hw/sw co-verification
1 61 Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-Random Test Program Generator
1 62 Isla: Integrating Full-Scale ISA Semantics and Axiomatic Concurrency Models (armstrong:cav:2021)
1 63 A Complete Formal Semantics of x86-64 User-Level ISA (dasgupta:pldi)
1 64 AFL++: Combining Incremental Steps of Fuzzing Research
1 65 RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption
1 66 End-to-End Verification of ARM Processors with ISA-Formal (reid:cav:2016)
1 67 The Pentium Bug, an Industry Watershed
1 68 Optimizing Design Verification using Machine Learning: Doing better than Random
1 69 Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
1 70 VeriDebug
1 71 Design Verification of the HP9000 Series 7000 PA-RISC Workstations
1 72 ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
1 73 Analyzing Partition Testing Strategies
1 74 MicroTESK: specification-based tool for constructing test program generators
1 75 DiveFuzz: Enhancing CPU Fuzzing via Diverse Instruction Construction
1 76 Theories of Program Testing and the Application of Revealing Subdomains
1 77 RVISmith: Fuzzing Compilers for RVV Intrinsics
1 78 Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities
1 79 Coverage Driven Processor Bug Classification
1 80 Towards Developing High Performance RISC-V Processors Using Agile Methodology
1 81 Design and Validation of Computer Protocols
1 82 Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
1 83 Functional Verification of the IBM System z10 Processor Chipset
1 84 SpecFuzz: Bringing Spectre-type vulnerabilities to the surface
1 85 Architecture Validation for Processors
1 86 WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors
1 87 VerilogEval: evaluating large language models for Verilog code generation
1 88 On a consistency testing model and strategy for revealing RISC processor's dark instructions and vulnerabilities
1 89 Algorithms for Constraint Satisfaction Problems: A Survey
1 90 SMT-based Stimuli Generation in SystemC Verification Library (Wille et al., 2009)
1 91 Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations (hsiao:micro:2021)
1 92 DifuzzRTL: Differential Fuzz Testing to Find CPU Bug (S&P 2021)
1 93 VeriContaminated: assessing LLM-driven Verilog coding for data contamination
1 94 Research on functional verification method processor model built by Chisel
1 95 Automatic Test Program Generation: A Case Study
1 96 Practical Approaches to SOC Verification
1 97 Constrained Random Test Environment for SoC Verification using VERA
1 98 Profuzz Paper
1 99 The Transaction-Based Verification Methodology
1 100 A reinforcement learning approach to directed test generation for shared memory verification
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