Paper
Paper
280 entities#
1 A Genetic Testing Framework for Digital Integrated Circuits
1 2 ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
1 3 Understanding the RISC-V Verification Ecosystem
1 4 RISC-V Processor Verification Requires the Full Toolbox
1 5 MicroTESK: specification-based tool for constructing test program generators
1 6 Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
1 7 Monadic Constraint Programming
1 8 AFL++: Combining Incremental Steps of Fuzzing Research
1 9 Reversi: Post-silicon validation system for modern microprocessors
1 10 PATARA: A REVERSI-based open-source tool for post-silicon validation of processor cores
1 11 Specification-based test program generation for MIPS64 memory management units
1 12 Top-level Validation of System-on-Chip in Esterel Studio
1 13 Practical Approaches to SOC Verification
1 14 Constrained Random Test Environment for SoC Verification using VERA
1 15 The Transaction-Based Verification Methodology
1 16 The Design and Implementation of a First-Generation CELL Processor
1 17 Quality-Driven SystemC Design
1 18 Program synthesis as latent continuous optimization
1 19 PSB2
1 20 The three pillars of machine programming
1 21 Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation
1 22 Solver Aided Reverse Engineering of Architectural Features (zorn:iscawddd:2017)
1 23 Automatic Test Program Generation: A Case Study
1 24 Modelling the ARMv8 Architecture Operationally: Concurrency and ISA (flur:popl:2016)
1 25 Verification Reference Cookbook for Bluespec RISC-V Processors
1 26 Instruction-Level Abstraction (ILA): A Uniform Specification for SoC Verification (huang:todaes:2019)
1 27 Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
1 28 SMT-Based Test Program Generation for Cache-Memory Testing
1 29 Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations (hsiao:micro:2021)
1 30 ReFuzz: Reusing Tests for Processor Fuzzing with Contextual Bandits
1 31 Fuzzilicon: A Post-Silicon Microcode-Guided x86 CPU Fuzzer
1 32 Automatic Generation and Validation of Instruction Encoders and Decoders (xu:cav:2021)
1 33 Who Guards the Guards? Formal Validation of the ARM v8-M Architecture Specification (reid:oopsla:2017)
1 34 Trustworthy Specifications of ARM v8-A and v8-M System Level Architecture (reid:fmcad:2016)
1 35 TurboFuzz Paper
1 36 Profuzz Paper
1 37 End-to-End Verification of ARM Processors with ISA-Formal (reid:cav:2016)
1 38 System-on-a-chip Verification – Methodology and Techniques
1 39 Isla: Integrating Full-Scale ISA Semantics and Axiomatic Concurrency Models (armstrong:cav:2021)
1 40 Detailed Models of ISAs: From Pseudocode to Formal Semantics (armstrong:arw:2018)
1 41 What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications
1 42 AVPGEN: Architecture Verification Program Generation for Processor Conformance Testing
1 43 AutoSVA: Democratizing Formal Verification of RTL Module Interactions
1 44 AutoCC: Automatic Covert Channel Discovery in Hardware
1 45 proGenesys: Program Generation Tool Based on Genetic Systems
1 46 Efficient Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration
1 47 SMT-based stimuli generation in the SystemC verification library
1 48 Test Program Generation for Memory Management Units of Microprocessors
1 49 UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model (Zachariasova et al.)
1 50 ProcessorFuzz
1 51 ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS (armstrong:popl19:2019)
1 52 Playing Atari with Deep Reinforcement Learning
1 53 Data constraint generation technology for microprocessor instruction verification based on SMT solver
1 54 Enhancing the efficiency of Bayesian network based coverage directed test generation
1 55 A reinforcement learning approach to directed test generation for shared memory verification
1 56 On a consistency testing model and strategy for revealing RISC processor's dark instructions and vulnerabilities
1 57 A Language and Preprocessor for User-Controlled Generation of Synthetic Programs
1 58 Integrated UVM-TLM Co-Simulation for RISC-V Verification
1 59 IEEE Design and Test of Computers
1 60 Cost evaluation of coverage directed test generation for the IBM mainframe
1 61 Survey of Verification of RISC-V Processors
1 62 UVM Verification of RISC-V Instruction Set
1 63 RISC-V UVM Verification Thesis
1 64 System-Level Verification of Multi-Core RISC-V
1 65 Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools
1 66 Fast Construction of Test-Program Generators for Digital Signal Processors
1 67 Open-source validation suite for RISC-V
1 68 Fuzzware: Using Precise MMIO Modeling for Effective Firmware Fuzzing
1 69 DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs
1 70 Who tests the TestRIG? Tooling for randomised tandem verification
1 71 Differential Analysis of x86-64 Instruction Decoders
1 72 Reverse-Engineering Instruction Encodings (hsieh:usenix:2001)
1 73 Simplifying ARM Concurrency: Multicopy-Atomic Axiomatic and Operational Models for ARMv8 (pulte:popl:2017)
1 74 Applying Constrained-Random Verification to Microprocessors
1 75 Coverage Driven Constraint Random Verification Architecture
1 76 Test Program Generation for Microprocessors
1 77 Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming
1 78 CMA-ES for one-class constraint synthesis
1 79 MicroGP — An Evolutionary Assembly Program Generator
1 80 Fully Automatic Test Program Generation for Microprocessor Cores
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