Paper
Paper
376 entities#
1 RISC-V Manual
2 2 Towards Efficient and Automated Side Channel Evaluations at Design Time
2 3 A General Framework for Hindley/Milner Type Systems with Constraints
2 4 TMDFI
2 5 HW/SW Co-Verification using Bounded Model Checking (Große et al., 2006)
2 6 Crafting a Million Instructions/Sec RISCV-DV
2 7 Automatic Constraint Generation for Guided Random Simulation (Yeh & Huang, 2010)
2 8 Piparazzi: A Test Program Generator for Micro-architecture Flow Verification
2 9 Graph-Based Functional Test Program Generation for Pipelined Processors
2 10 Functional Test Generation using SAT-based Bounded Model Checking
2 11 GoldenFuzz: A Novel Two-Stage Hardware Fuzzing Framework
2 12 AFL White-Paper
2 13 DiFuzzRTL Paper
2 14 RISC-V Instruction Set Manual Volume I
2 15 Model Based Test Generation for Processor Verification
2 16 RISC-V Debug Specification
2 17 SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels
2 18 CORE-V Verification Strategy
2 19 DeepTrans - A Model-Based Approach to Functional Verification of Address Translation Mechanisms
2 20 DAPO: an open-source LLM reinforcement learning system at scale
2 21 A Hybrid Verification Solution to RISC-V Vector Extension (C. Li et al.)
2 22 Testbench Flexibility as a Foundation for Success (A.S. Carretero et al.)
2 23 Universal fuzzing via large language models
2 24 BugGen: a self-correcting multi-agent LLM pipeline for realistic RTL bug synthesis
2 25 Comprehensive Verilog Design Problems (CVDP) benchmark
2 26 TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
2 27 Decomposed prompting: a modular approach for solving complex tasks
2 28 Handcrafted Inversions Made Operational on Operational Semantics
2 29 seL4: Formal Verification of an OS Kernel
2 30 Functional Verification of the POWER5 Microprocessor and POWER5 Multiprocessor Systems
2 31 Industrial Experience with Test Generation Languages for Processor Verification
2 32 Assumption-based Pruning in Conditional CSP
2 33 Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation
2 34 FloppyFloat: An open source floating point library for instruction set simulators
2 35 RISC-V VP++: Next generation open-source virtual prototype
2 36 HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
2 37 Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
2 38 Advanced Verification Suite for RISC-V Cores
2 39 ISA semantics for ARMv8-a, RISC-V, and CHERI-MIPS
2 40 A Complete Formal Semantics of x86-64 User-level Instruction Set Architecture
2 41 catnap: Generating Test Suites of Constrained Combinatorial Testing with Answer Set Programming
2 42 StarCoder 2 and The Stack v2: The Next Generation
2 43 Specification-Driven Directed Test Generation for Validation of Pipelined Processors
2 44 The PowerPC Architecture
1 45 PATARA: A REVERSI-based open-source tool for post-silicon validation of processor cores
1 46 Reversi: Post-silicon validation system for modern microprocessors
1 47 Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
1 48 MicroTESK: specification-based tool for constructing test program generators
1 49 ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
1 50 Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
1 51 Optimizing Design Verification using Machine Learning: Doing better than Random
1 52 A Complete Formal Semantics of x86-64 User-Level ISA (dasgupta:pldi)
1 53 Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic
1 54 Hybrid Intelligent Testing in Simulation-Based Verification
1 55 Comprehensive RISC-V floating-point verification: Efficient coverage models and constraint-based test generation
1 56 Automated Synthesis of Symbolic Instruction Encodings from I/O Samples (godefroid:pldi:2012)
1 57 Directing greybox fuzzing to discover bugs in hardware and software
1 58 Proceedings Article 2025-10-26
1 59 Micro-Architecture Coverage Directed Generation of Test Programs
1 60 Test Program Generation for Microprocessors
1 61 Simplifying ARM Concurrency: Multicopy-Atomic Axiomatic and Operational Models for ARMv8 (pulte:popl:2017)
1 62 Reverse-Engineering Instruction Encodings (hsieh:usenix:2001)
1 63 Who tests the TestRIG? Tooling for randomised tandem verification
1 64 Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools
1 65 ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS (armstrong:popl19:2019)
1 66 ProcessorFuzz
1 67 Test Program Generation for Memory Management Units of Microprocessors
1 68 Efficient Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration
1 69 What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications
1 70 Detailed Models of ISAs: From Pseudocode to Formal Semantics (armstrong:arw:2018)
1 71 Isla: Integrating Full-Scale ISA Semantics and Axiomatic Concurrency Models (armstrong:cav:2021)
1 72 End-to-End Verification of ARM Processors with ISA-Formal (reid:cav:2016)
1 73 Trustworthy Specifications of ARM v8-A and v8-M System Level Architecture (reid:fmcad:2016)
1 74 Who Guards the Guards? Formal Validation of the ARM v8-M Architecture Specification (reid:oopsla:2017)
1 75 Automatic Generation and Validation of Instruction Encoders and Decoders (xu:cav:2021)
1 76 Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations (hsiao:micro:2021)
1 77 Instruction-Level Abstraction (ILA): A Uniform Specification for SoC Verification (huang:todaes:2019)
1 78 Modelling the ARMv8 Architecture Operationally: Concurrency and ISA (flur:popl:2016)
1 79 Solver Aided Reverse Engineering of Architectural Features (zorn:iscawddd:2017)
1 80 Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation
1 81 The three pillars of machine programming
1 82 Program synthesis as latent continuous optimization
1 83 PSB2
1 84 Automatic Test Program Generation: A Case Study
1 85 Verification Reference Cookbook for Bluespec RISC-V Processors
1 86 SMT-Based Test Program Generation for Cache-Memory Testing
1 87 ReFuzz: Reusing Tests for Processor Fuzzing with Contextual Bandits
1 88 Fuzzilicon: A Post-Silicon Microcode-Guided x86 CPU Fuzzer
1 89 TurboFuzz Paper
1 90 Profuzz Paper
1 91 VerilogEval: evaluating large language models for Verilog code generation
1 92 VeriDebug
1 93 AVPGEN: Architecture Verification Program Generation for Processor Conformance Testing
1 94 AutoSVA: Democratizing Formal Verification of RTL Module Interactions
1 95 AutoCC: Automatic Covert Channel Discovery in Hardware
1 96 proGenesys: Program Generation Tool Based on Genetic Systems
1 97 DeepSeekMath: pushing the limits of mathematical reasoning in open language models
1 98 RTLLM: an open-source benchmark for design RTL generation with large language model
1 99 UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model (Zachariasova et al.)
1 100 Playing Atari with Deep Reinforcement Learning
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