Paper
Paper
388 entities#
1 Enhancing the efficiency of Bayesian network based coverage directed test generation
1 2 TurboFuzz Paper
1 3 Automatic Generation and Validation of Instruction Encoders and Decoders (xu:cav:2021)
1 4 IEEE Xplore Full-Text PDF
1 5 Data constraint generation technology for microprocessor instruction verification based on SMT solver
1 6 ProcessorFuzz
1 7 Xiangshan MICRO 2022 Paper
1 8 Verification Reference Cookbook for Bluespec RISC-V Processors
1 9 Trustworthy Specifications of ARM v8-A and v8-M System Level Architecture (reid:fmcad:2016)
1 10 Playing Atari with Deep Reinforcement Learning
1 11 System-on-a-chip Verification – Methodology and Techniques
1 12 Test Program Generation for Memory Management Units of Microprocessors
1 13 UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model (Zachariasova et al.)
1 14 Nuts and Bolts of Core and SoC Verification
1 15 Top-level Validation of System-on-Chip in Esterel Studio
1 16 The Design and Implementation of a First-Generation CELL Processor
1 17 Finite-Time Analysis of the Multiarmed Bandit Problem
1 18 Fuzzilicon: A Post-Silicon Microcode-Guided x86 CPU Fuzzer
1 19 Efficient Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration
1 20 What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications
1 21 Reversi: Post-silicon validation system for modern microprocessors
1 22 Quality-Driven SystemC Design
1 23 SMT-based stimuli generation in the SystemC verification library
1 24 Formally Verifying a Microprocessor Using a Simulation Methodology
1 25 Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures
1 26 Integrated Design and Test Assistance for Pipeline Controllers
1 27 The PowerPC Architecture
1 28 POWER and PowerPC
1 29 A Processor Implementation Verification Methodology
1 30 Directed Test Generation for Hardware Validation: A Survey (ACM CS 2023)
1 31 RTLLM: an open-source benchmark for design RTL generation with large language model
1 32 DeepSeekMath: pushing the limits of mathematical reasoning in open language models
1 33 Detailed Models of ISAs: From Pseudocode to Formal Semantics (armstrong:arw:2018)
1 34 proGenesys: Program Generation Tool Based on Genetic Systems
1 35 PATARA: A REVERSI-based open-source tool for post-silicon validation of processor cores
1 36 Who Guards the Guards? Formal Validation of the ARM v8-M Architecture Specification (reid:oopsla:2017)
1 37 Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation
1 38 Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools
1 39 Applying Constrained-Random Verification to Microprocessors
1 40 Coverage Driven Constraint Random Verification Architecture
1 41 Differential Analysis of x86-64 Instruction Decoders
1 42 Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming
1 43 SMT-Based Test Program Generation for Cache-Memory Testing
1 44 Solver Aided Reverse Engineering of Architectural Features (zorn:iscawddd:2017)
1 45 CMA-ES for one-class constraint synthesis
1 46 MicroGP — An Evolutionary Assembly Program Generator
1 47 Fully Automatic Test Program Generation for Microprocessor Cores
1 48 GenHuzz paper
1 49 ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS (armstrong:popl19:2019)
1 50 Fuzzware: Using Precise MMIO Modeling for Effective Firmware Fuzzing
1 51 Open-source validation suite for RISC-V
1 52 Modelling the ARMv8 Architecture Operationally: Concurrency and ISA (flur:popl:2016)
1 53 Who tests the TestRIG? Tooling for randomised tandem verification
1 54 AutoCC: Automatic Covert Channel Discovery in Hardware
1 55 Lost in Translation: Enabling Confused Deputy Attacks on EDA Software with TransFuzz
1 56 Fast Construction of Test-Program Generators for Digital Signal Processors
1 57 System-Level Verification of Multi-Core RISC-V
1 58 Reverse-Engineering Instruction Encodings (hsieh:usenix:2001)
1 59 Simplifying ARM Concurrency: Multicopy-Atomic Axiomatic and Operational Models for ARMv8 (pulte:popl:2017)
1 60 Test Program Generation for Microprocessors
1 61 Micro-Architecture Coverage Directed Generation of Test Programs
1 62 The three pillars of machine programming
1 63 Proceedings Article 2025-10-26
1 64 Directing greybox fuzzing to discover bugs in hardware and software
1 65 Icicle: A Re-Designed Emulator for Grey-Box Firmware Fuzzing
1 66 AutoSVA: Democratizing Formal Verification of RTL Module Interactions
1 67 User Defined Coverage—A Tool Supported Methodology for Design Verification
1 68 Proximal Policy Optimization Algorithms
1 69 Adaptive Test Program Generation (US 2003/0130813 A1)
1 70 AVPGEN — A Test Case Generator for Architecture Verification
1 71 Symbolic Model Checking
1 72 The SMV System DRAFT
1 73 Architectural Verification of Processors Using Symbolic Instruction Graphs
1 74 RISC-V UVM Verification Thesis
1 75 Writing Testbenches: Functional Verification of HDL Models
1 76 UVM Verification of RISC-V Instruction Set
1 77 Hole analysis for functional coverage data
1 78 Microprocessor design verification by two-phase evolution of variable length tests
1 79 A Genetic Testing Framework for Digital Integrated Circuits
1 80 Program synthesis as latent continuous optimization
1 81 Automated Synthesis of Symbolic Instruction Encodings from I/O Samples (godefroid:pldi:2012)
1 82 Survey of Verification of RISC-V Processors
1 83 Cost evaluation of coverage directed test generation for the IBM mainframe
1 84 IEEE Design and Test of Computers
1 85 Metamorphic testing for processor verification: A RISC-V case study at the instruction level
1 86 PSB2
1 87 Integrated UVM-TLM Co-Simulation for RISC-V Verification
1 88 Automatic Test Program Generation for Pipelined Processors
1 88 of 388 shown
← prev page 4 of 4