Paper
Paper
376 entities#
1 Data constraint generation technology for microprocessor instruction verification based on SMT solver
1 2 Enhancing the efficiency of Bayesian network based coverage directed test generation
1 3 A reinforcement learning approach to directed test generation for shared memory verification
1 4 VeriContaminated: assessing LLM-driven Verilog coding for data contamination
1 5 On a consistency testing model and strategy for revealing RISC processor's dark instructions and vulnerabilities
1 6 A Language and Preprocessor for User-Controlled Generation of Synthetic Programs
1 7 Integrated UVM-TLM Co-Simulation for RISC-V Verification
1 8 IEEE Design and Test of Computers
1 9 Cost evaluation of coverage directed test generation for the IBM mainframe
1 10 Survey of Verification of RISC-V Processors
1 11 UVM Verification of RISC-V Instruction Set
1 12 RISC-V UVM Verification Thesis
1 13 System-Level Verification of Multi-Core RISC-V
1 14 Fast Construction of Test-Program Generators for Digital Signal Processors
1 15 Open-source validation suite for RISC-V
1 16 Fuzzware: Using Precise MMIO Modeling for Effective Firmware Fuzzing
1 17 Differential Analysis of x86-64 Instruction Decoders
1 18 Applying Constrained-Random Verification to Microprocessors
1 19 Coverage Driven Constraint Random Verification Architecture
1 20 Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming
1 21 CMA-ES for one-class constraint synthesis
1 22 MicroGP — An Evolutionary Assembly Program Generator
1 23 Fully Automatic Test Program Generation for Microprocessor Cores
1 24 User Defined Coverage—A Tool Supported Methodology for Design Verification
1 25 Adaptive Test Program Generation (US 2003/0130813 A1)
1 26 AVPGEN — A Test Case Generator for Architecture Verification
1 27 Symbolic Model Checking
1 28 The SMV System DRAFT
1 29 Architectural Verification of Processors Using Symbolic Instruction Graphs
1 30 Writing Testbenches: Functional Verification of HDL Models
1 31 Hole analysis for functional coverage data
1 32 Microprocessor design verification by two-phase evolution of variable length tests
1 33 A Genetic Testing Framework for Digital Integrated Circuits
1 34 Automatic Test Program Generation for Pipelined Processors
1 35 CHIA arXiv paper (arXiv:2606.27350)
1 36 Monadic Constraint Programming
1 37 Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-Random Test Program Generator
1 38 AFL++: Combining Incremental Steps of Fuzzing Research
1 39 The Pentium Bug, an Industry Watershed
1 40 Design Verification of the HP9000 Series 7000 PA-RISC Workstations
1 41 Analyzing Partition Testing Strategies
1 42 DiveFuzz: Enhancing CPU Fuzzing via Diverse Instruction Construction
1 43 Theories of Program Testing and the Application of Revealing Subdomains
1 44 RVISmith: Fuzzing Compilers for RVV Intrinsics
1 45 Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities
1 46 Coverage Driven Processor Bug Classification
1 47 Design and Validation of Computer Protocols
1 48 SpecFuzz: Bringing Spectre-type vulnerabilities to the surface
1 49 Architecture Validation for Processors
1 50 DifuzzRTL: Differential Fuzz Testing to Find CPU Bug (S&P 2021)
1 51 Practical Approaches to SOC Verification
1 52 Constrained Random Test Environment for SoC Verification using VERA
1 53 The Transaction-Based Verification Methodology
1 54 System-on-a-chip Verification – Methodology and Techniques
1 55 Nuts and Bolts of Core and SoC Verification
1 56 Top-level Validation of System-on-Chip in Esterel Studio
1 57 The Design and Implementation of a First-Generation CELL Processor
1 58 Quality-Driven SystemC Design
1 59 SMT-based stimuli generation in the SystemC verification library
1 60 Formally Verifying a Microprocessor Using a Simulation Methodology
1 61 Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures
1 62 Integrated Design and Test Assistance for Pipeline Controllers
1 63 POWER and PowerPC
1 64 A Processor Implementation Verification Methodology
1 65 GenHuzz paper
1 66 Lost in Translation: Enabling Confused Deputy Attacks on EDA Software with TransFuzz
1 67 Functional Verification of the IBM System z10 Processor Chipset
1 68 WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors
1 69 SMT-based Stimuli Generation in SystemC Verification Library (Wille et al., 2009)
1 70 Research on functional verification method processor model built by Chisel
1 71 Xiangshan MICRO 2022 Paper
1 72 Algorithms for Constraint Satisfaction Problems: A Survey
1 73 IEEE Xplore Full-Text PDF
1 74 Proximal Policy Optimization Algorithms
1 75 Between MDPs and Semi-MDPs: A Framework for Temporal Abstraction in Reinforcement Learning
1 76 Finite-Time Analysis of the Multiarmed Bandit Problem
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