00

Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation

Paper ☆ WATCH ⎘ SHARE

First seen 6/9/2026

Last seen 6/9/2026

Evidence 1 chunks

01

NEIGHBORHOOD

14 nodes · 19 edges

graph · Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation · depth=1

02

RELATIONSHIPS

13 connections

Kevin Martin authored by → 100% 1e evidence

Kevin Martin is listed as an author of the paper.

Christophe Wolinski authored by → 100% 1e evidence

Christophe Wolinski is listed as an author of the paper.

Krzysztof Kuchcinski authored by → 100% 1e evidence

Krzysztof Kuchcinski is listed as an author of the paper.

Antoine Floch authored by → 100% 1e evidence

Antoine Floch is listed as an author of the paper.

Francois Charot authored by → 100% 1e evidence

Francois Charot is listed as an author of the paper.

IFPEC introduces → 100% 1e evidence

The paper presents IFPEC as its integrated design framework.

Constraint Programming uses → 100% 1e evidence

The paper presents a constraint programming approach for processor extension design problems.

Processor Extensions uses → 100% 1e evidence

The paper addresses automatic selection and synthesis of processor extensions.

Custom Instructions uses → 100% 1e evidence

The paper discusses custom instructions implemented as processor extensions.

Runtime Reconfigurable Cells uses → 100% 1e evidence

The paper assumes architectures composed of runtime reconfigurable cells.

Reconfigurable Processor uses → 90% 1e evidence

The paper targets reconfigurable processor architectures.

Graph Representation uses → 100% 1e evidence

The paper uses graph representation for both custom instructions and application modeling.

Subgraph Isomorphism uses → 100% 1e evidence

The paper uses subgraph isomorphism constraints for processor extension identification.