System-Level Verification of Multi-Core RISC-V

Paper

First seen 7/6/2026

Last seen 7/6/2026

Evidence 1 chunks

NEIGHBORHOOD

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4 connections

The paper uses Spike ISS as a reference model for multi-core RISC-V verification.

riscv-dv uses → 97% 1e

The paper uses RISCV-DV for generating random instruction binaries.

Directed Testing uses → 95% 1e

The paper employs directed tests in addition to random testing.

RISC-V evaluates → 97% 1e

The paper presents a verification strategy for a multi-core RISC-V system.