TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
PaperFirst seen 5/30/2026
Last seen 6/5/2026
Evidence 2 chunks
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12 connectionsThe paper discusses simulation-based approaches and their limitations.
The paper introduces TurboFuzz as its primary contribution.
The paper mentions ISAs as a driver for new verification needs.
Haoran Wu submitted the paper and is listed as a corresponding author.
The paper mentions RISC-V as a new ISA driving demand for agile verification.
Yang Zhong is listed as an author of the paper.
The paper mentions ASIC platforms as hardware-accelerated alternatives for verification.
The paper identifies host-FPGA communication overhead as a challenge in existing solutions.
The paper highlights faster coverage convergence as a key motivation and contribution.
The paper identifies inefficient test pattern generation as a challenge for existing solutions.
The paper mentions ASIC platforms as hardware-accelerated solutions for verification.
The paper presents experimental results evaluating TurboFuzz's performance.