Host-FPGA Communication Overhead
ConceptHost-FPGA communication overhead is identified in the TurboFuzz paper as one of the limitations of prior FPGA- or ASIC-based hardware-accelerated processor verification approaches. The paper positions TurboFuzz as an end-to-end framework that places the full Test Generation-Simulation-Coverage Feedback loop on a single FPGA, in part to avoid this and related workflow inefficiencies.
WIKI
Overview
Host-FPGA communication overhead refers to the communication cost between a host system and an FPGA in hardware-accelerated verification workflows. In the TurboFuzz paper, it is named as one of the challenges that limits prior hardware-accelerated solutions for processor verification.
In TurboFuzz
TurboFuzz describes existing FPGA- or ASIC-based approaches as struggling with host-FPGA communication overhead, along with inefficient test pattern generation and suboptimal implementation of the entire multi-step verification process.
As a response, TurboFuzz presents an end-to-end hardware-accelerated verification framework that implements the entire Test Generation-Simulation-Coverage Feedback loop on a single FPGA.
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