Optimizing Design Verification using Machine Learning: Doing better than Random

Paper

First seen 6/2/2026

Last seen 6/3/2026

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RELATIONSHIPS

27 connections

RISC-V Random Instruction Generator uses → 100% 3e

The paper uses Google's RISCV Random Instruction Generator as part of the RISCV-Ariane verification example.

Sandeep Srinivasan authored by → 100% 3e

Sandeep Srinivasan submitted the paper on behalf of the authors.

Cache Controller evaluates → 100% 2e

One of the two hardware verification examples presented in the paper is a Cache Controller design.

Constrained Random Stimulus uses → 100% 2e

The paper describes an approach that leverages constrained-random stimulus as a baseline DV technique.

Reinforcement Learning uses → 100% 2e

The paper enhances the DV environment using reinforcement learning techniques.

Supervised Learning uses → 100% 2e

The paper enhances the DV environment using supervised learning techniques.

Functional Coverage evaluates → 100% 2e

The paper evaluates its approach by measuring functional coverage improvements over random methods.

Reinforcement Learning uses → 100% 1e

The paper enhances constrained-random DV using reinforcement learning techniques.

Constrained Random Stimulus uses → 100% 1e

The paper leverages existing constrained-random DV environment tools as a baseline approach.

RISCV-Ariane uses → 100% 1e

The paper uses the open-source RISCV-Ariane design as one of its hardware verification examples.

design verification mentions → 100% 1e

Design verification is the central topic and motivation of the paper.

Integrated Circuits mentions → 100% 1e

The paper mentions increasing complexity of integrated circuits as motivation for its approach.

Machine Learning for Hardware Verification introduces → 95% 1e

The paper introduces a machine-learning based approach to hardware design verification.

Constrained Random DV Environment uses → 95% 1e

The paper's approach leverages existing constrained-random DV environment tools.

RISCV-Ariane evaluates → 97% 1e

The paper presents a hardware verification example using the open-source RISCV-Ariane design.

Cache Controller Design evaluates → 97% 1e

The paper presents a hardware verification example of a Cache Controller design.

Machine Learning for Verification uses → 99% 1e

The paper's core contribution is applying machine learning to design verification.

Functional Coverage uses → 97% 1e

The paper demonstrates better performance on functional coverage than random or constrained-random approaches.

Coverage Points uses → 95% 1e

The paper focuses on hitting all possible design coverage points as a DV objective.

William Hughes authored by → 100% 1e

William Hughes is listed as an author of the paper.

design verification uses → 100% 1e

Design Verification is the core domain of the paper.

Machine Learning uses → 100% 1e

The paper leverages machine learning to optimize design verification.

design verification evaluates → 100% 1e

The paper evaluates machine learning approaches applied to design verification.

RISCV-Ariane evaluates → 100% 1e

The paper uses RISCV-Ariane as a hardware verification example to evaluate the proposed approach.

Coverage Points mentions → 100% 1e

The paper mentions design coverage points as the key objective of design verification.

Integrated Circuit Design mentions → 100% 1e

The paper mentions integrated circuits as the subject whose increasing complexity motivates the work.

Supervised Learning uses → 100% 1e

The paper enhances constrained-random DV using supervised learning techniques.