Cache Controller Design

Concept

A Cache Controller Design is a hardware design used in integrated circuits that, in the cited evidence, served as one of two benchmark hardware verification examples in a study on applying supervised learning and reinforcement learning techniques to improve constrained-random Design Verification (DV) environments.

First seen 6/3/2026

Last seen 6/3/2026

Evidence 1 chunks

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WIKI

Overview

A Cache Controller Design is a hardware module used within integrated circuits to manage the operation of cache memory, including handling reads, writes, evictions, coherence, and address translation between processor cores and memory hierarchies. Within the cited evidence, a Cache Controller design appears specifically as a benchmark example used to demonstrate the application of machine learning techniques to functional verification rather than being the primary subject of the paper.

Role in the Cited Verification Study

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RELATIONSHIPS

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Optimizing Design Verification using Machine Learning: Doing better than Random ← evaluates 97% 1e

The paper presents a hardware verification example of a Cache Controller design.

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Optimizing Design Verification using Machine Learning: Doing better than Random EVALUATES Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] A Cache Controller design is presented in arXiv:1909.13168v1 as one of two hardware verification examples used to evaluate an ML-based constrained-random Design Verification approach. Optimizing Design Verification using Machine Learning: Doing better than Random

[2] The other hardware verification example in the paper is the open-source RISC-V Ariane design paired with Google's RISC-V Random Instruction Generator. Optimizing Design Verification using Machine Learning: Doing better than Random

[3] The paper demonstrates that the machine-learning based approach performs significantly better than a random or constrained-random approach on functional coverage and reaching complex hard-to-hit states for the Cache Controller benchmark. Optimizing Design Verification using Machine Learning: Doing better than Random

[4] The paper was submitted to arXiv on 28 September 2019 by William Hughes and three other authors, with Sandeep Srinivasan listed as a contact author. Optimizing Design Verification using Machine Learning: Doing better than Random