Coverage Points

Concept

Coverage points are verification targets used to assess whether a design has exercised desired behaviors, combinations, or states during testing. In the cited hardware design verification paper, hitting all possible design coverage points is presented as a major verification bottleneck for complex designs, especially when random or constrained-random stimulus struggles to reach hard-to-hit scenarios.

First seen 6/2/2026

Last seen 6/3/2026

Evidence 1 chunks

Wiki v1

WIKI

Coverage Points

In the provided evidence, coverage points appear in the context of hardware design verification (DV). They refer to the targets that a verification process aims to hit so that the design's functionality is adequately exercised during testing.^[1]

Role in design verification

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

Optimizing Design Verification using Machine Learning: Doing better than Random ← mentions 100% 1e

The paper mentions design coverage points as the key objective of design verification.

Optimizing Design Verification using Machine Learning: Doing better than Random ← uses 95% 1e

The paper focuses on hitting all possible design coverage points as a DV objective.

LINKED ENTITIES

1 links

Optimizing Design Verification using Machine Learning: Doing better than Random MENTIONS Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Coverage points are used in the evidence as verification targets in hardware design verification. Optimizing Design Verification using Machine Learning: Doing better than Random

[2] Purely random stimulus can theoretically exercise all combinations, but in practice it struggles to do so in a timely fashion for highly complex designs. Optimizing Design Verification using Machine Learning: Doing better than Random

[3] The verification time required to hit all possible design coverage points is described as a dominant schedule limitation as designs become more complex. Optimizing Design Verification using Machine Learning: Doing better than Random

[4] The paper proposes supervised learning and reinforcement learning to enhance constrained-random DV and help achieve full design coverage more quickly and with fewer resources. Optimizing Design Verification using Machine Learning: Doing better than Random

[5] The paper reports improved functional coverage and better reachability of complex hard-to-hit states relative to random or constrained-random approaches. Optimizing Design Verification using Machine Learning: Doing better than Random