Constrained Random Stimulus

Technique

Constrained Random Stimulus is a hardware design verification technique that steers a random stimulus generator toward hard-to-hit input combinations via user-defined constraints, combining the breadth of random testing with targeted exploration of the design state space.

First seen 6/3/2026

Last seen 6/3/2026

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Overview

Constrained Random Stimulus is a widely adopted technique in hardware Design Verification (DV). In contrast to purely directed testbenches—where each stimulus is hand-written—constrained random stimulus generation automatically produces test vectors, while user-supplied constraints bias the generator toward the regions of the input space that are of greatest verification interest. As integrated circuits have grown more complex, this constrained-random approach has become ubiquitous as a means of stimulating a design's functionality and ensuring it fully meets expectations [chunk:bdde8a58-b6fc-4ae6-a7d5-3e78f5f57d45].

Motivation

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Optimizing Design Verification using Machine Learning: Doing better than Random ← uses 100% 1e

The paper leverages existing constrained-random DV environment tools as a baseline approach.

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Optimizing Design Verification using Machine Learning: Doing better than Random USES Extracted graph relationship

CITATIONS

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6 citations — click to expand

[1] Constrained random stimulus is ubiquitous as a means of stimulating a design's functionality and ensuring it fully meets expectations. Optimizing Design Verification using Machine Learning: Doing better than Random

[2] In theory, random stimulus allows all possible combinations to be exercised given enough time, but in practice with highly complex designs a purely random approach will have difficulty exercising all possible combinations in a timely fashion. Optimizing Design Verification using Machine Learning: Doing better than Random

[3] It is often necessary to steer the Design Verification (DV) environment to generate hard-to-hit combinations, yielding a constrained-random approach that relies on extensive human expertise. Optimizing Design Verification using Machine Learning: Doing better than Random

[4] As designs become more complex, the guidance aspect of constrained random stimulus becomes progressively more challenging and time-consuming, often making verification time the dominant schedule limitation. Optimizing Design Verification using Machine Learning: Doing better than Random

[5] Constrained-random DV environments can be enhanced using supervised learning and reinforcement learning techniques to provide better-than-random results in a highly automated fashion. Optimizing Design Verification using Machine Learning: Doing better than Random

[6] A machine-learning-based approach can perform significantly better on functional coverage and reaching complex hard-to-hit states than a random or constrained-random approach, as demonstrated on a Cache Controller design and on the open-source RISC-V Ariane design with Google's RISC-V Random Instruction Generator. Optimizing Design Verification using Machine Learning: Doing better than Random