Machine Learning for Test Generation
ConceptMachine learning for test generation is evidenced here as a coverage-guided test-generation approach that includes Bayesian-network-based methods and other machine-learning techniques, discussed in the context of processor and RISC-V verification.
First seen 5/26/2026
Last seen 5/30/2026
Evidence 2 chunks
Wiki v1
WIKI
Overview
Machine Learning for Test Generation refers, in the available evidence, to automated test-generation techniques that use machine-learning methods as part of a coverage-guided workflow. The source explicitly identifies coverage-guided test generation based on Bayesian networks and on other machine-learning techniques as part of the test-generation landscape for processor verification. [C1]
Position in processor-verification test generation
NEIGHBORHOOD
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2 connectionsThe paper mentions machine learning techniques as related work for test generation.
Machine learning for test generation is mentioned as an alternative approach compared to coverage-guided aging.
LINKED ENTITIES
3 linksBayesian Networks uses_technique The evidence explicitly mentions coverage-guided test generation based on Bayesian networks.
coverage-guided test generation is_form_of The evidence frames Bayesian-network and other machine-learning techniques as coverage-guided test generation.
Symbolic Execution related_test_generation_approach The evidence states that formal methods based on symbolic execution have been used for test-case generation at the ISS level.
CITATIONS
3 sources3 citations — click to collapse
[1] Machine-learning-based test generation includes coverage-guided generation based on Bayesian networks and other machine-learning techniques. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[2] The processor-verification landscape includes directed RISC-V test suites, randomized-pattern instruction generation, constraint-based specifications, symbolic-execution-based test-case generation, fuzzing-based emulator testing, and LLVM-libFuzzer-based RISC-V ISS verification. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[3] AFL is an out-of-process coverage-guided grey-box fuzzer that uses edge coverage, trimming, and mutations including bitflip, arithmetic, and havoc mutations. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing