Industrial Experience with Test Generation Languages for Processor Verification

Paper

“Industrial Experience with Test Generation Languages for Processor Verification” is a 2004 paper by M. Behm, J. Ludden, Y. Lichtenstein, M. Rimon, and M. Vinov, published in the 41st Design Automation Conference (DAC’04), pages 36–40. It is cited in evidence about IBM’s Genesys PE processor-verification work as supporting the test-template rule-definition language used to describe complex verification scenarios.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Industrial Experience with Test Generation Languages for Processor Verification is listed as a 2004 paper by M. Behm, J. Ludden, Y. Lichtenstein, M. Rimon, and M. Vinov. The reference entry places it in the 41st Design Automation Conference (DAC’04), pages 36–40.

Technical context

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RELATIONSHIPS

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Test Template Language mentions → 90% 1e

The paper discusses industrial experience with test generation languages which includes the test template language.

LINKED ENTITIES

2 links

Genesys PE technical_context The evidence cites Behm et al. (2004) in the discussion of Genesys PE's test-template rule-definition language and compares Genesys PE with Genesys.

Genesys compared_system The evidence contrasts Genesys PE with the earlier Genesys test-generation technology in productivity and scenario expressiveness.

CITATIONS

5 sources

5 citations — click to expand

[1] The paper is authored by M. Behm, J. Ludden, Y. Lichtenstein, M. Rimon, and M. Vinov and was published in 2004. [PDF] Constraint-Based Random Stimuli Generation for Hardware ... - AAAI

[2] The paper appeared in the 41st Design Automation Conference (DAC’04), pages 36–40. [PDF] Constraint-Based Random Stimuli Generation for Hardware ... - AAAI

[3] Behm et al. (2004) is cited in connection with a new test-template rule-definition language that provides programming constructs for describing complex verification scenarios in general form. [PDF] Constraint-Based Random Stimuli Generation for Hardware ... - AAAI

[4] The Genesys PE discussion reports CSP-based test generation as expanding the space of verifiable scenarios compared with Genesys, including conjunctive-constraint scenarios. [PDF] Constraint-Based Random Stimuli Generation for Hardware ... - AAAI

[5] The surrounding IBM account reports Genesys PE improvements in productivity, verification quality, verification processes, and operational costs. [PDF] Constraint-Based Random Stimuli Generation for Hardware ... - AAAI