Overview

Industrial Experience with Test Generation Languages for Processor Verification is listed as a 2004 paper by M. Behm, J. Ludden, Y. Lichtenstein, M. Rimon, and M. Vinov. The reference entry places it in the 41st Design Automation Conference (DAC’04), pages 36–40.

Technical context

The paper is cited in a discussion of Genesys PE, IBM’s next-generation processor stimuli generator, in the context of improvements over the earlier Genesys test-generation technology. The cited discussion states that Genesys PE used CSP-based test generation technology to expand the space of verifiable scenarios compared with Genesys, including scenarios with conjunctive constraints such as satisfying conditions for multiple exceptions.

Within that same discussion, Behm et al. (2004) is specifically cited for a test-template rule-definition language that provides a broad set of programming constructs. The reported purpose of those constructs was to allow complex verification scenarios to be described in a more general form; the source contrasts this with Genesys, where only a subset of such scenarios could be written and those scenarios did not always cover desired events.

Reported industrial relevance

The surrounding IBM account reports several industrial outcomes for Genesys PE: a more compact test suite than Genesys, broader scenario generation through CSP-based technology, design-independent scenario descriptions, and reduced verification staffing requirements. While these outcomes are reported for Genesys PE as an application, the Behm et al. paper is cited specifically in relation to the rule-definition language capability used to express complex scenarios.