Research on functional verification method processor model built by Chisel
PaperFirst seen 8/6/2026
Last seen 8/6/2026
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11 connectionsLening WU is listed as a co-author of the paper.
Miao WANG is listed as a co-author of the paper.
Fu CHEN is listed as a co-author of the paper.
The paper presents a functional verification methodology applied to the ARMChisel processor model.
The paper designs and uses a random instruction generator supporting all ARM V4 ISA instructions.
The paper proposes and applies functional verification methods to the processor model.
The paper uses coverage-driven verification as one of its verification stages.
The paper employs direct test verification as one of its verification stages.
The paper uses FPGA acceleration to verify large-scale applications and shorten the verification cycle.
The paper builds test platforms in both the Chisel environment and the Verilog environment.
The paper uses the Chisel hardware language environment to build test platforms and verify the processor model.