Chisel
ToolChisel is a hardware description/construction language embedded in Scala, used to generate RTL (Verilog) for RISC-V processors and accelerators. It powers open-source projects including BOOM, Rocket Chip, Gemmini, and the XiangShan Kunminghu architecture, and is the hardware-description language targeted by the UnityChipForXiangShan verification framework. The name 'Chisel' is also used by an unrelated Go-based TCP/UDP tunneling tool (jpillora/chisel).
First seen 5/27/2026
Last seen 8/11/2026
Evidence 11 chunks
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WIKI
Overview
The name Chisel appears in two distinct contexts in the provided evidence:
- Chisel hardware construction language — an HDL embedded in Scala, used to generate Verilog for RISC-V cores, accelerators, and other digital designs. This is the dominant and most relevant meaning given the related entities and supporting evidence.
- jpillora/chisel — a separate Go-based tool described as "a fast TCP/UDP tunnel over HTTP," not connected to the hardware-construction language by the supplied evidence.
NEIGHBORHOOD
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explore full graph →RELATIONSHIPS
8 connectionsChiffre automatically instruments hardware systems written in Chisel.
Rocket Core was generated using Chisel hardware generator
PORTRUSH compiles Chisel source code of RISC-V CPUs for analysis.
Participants in UnityChipForXiangShan learn the Chisel hardware description language used in XiangShan.
Chisel is a domain-specific language that raises abstraction level for hardware design, supporting agile chip design
The ARMChisel processor model is built using the Chisel hardware language.
The paper uses the Chisel hardware language environment to build test platforms and verify the processor model.
CFC is built for Chisel-based hardware designs.
LINKED ENTITIES
1 linksCITATIONS
11 sources11 citations — click to expand
[1] Chisel is an HDL embedded into the Scala programming language, allowing Scala software elements to interact with Chisel hardware elements without a DPI-type connection. Design and Application of a Co-Simulation Framework for Chisel
[2] Chisel groups with TL Verilog and Bluespec as a higher-level hardware-description DSL that raises the abstraction level of both design and verification. ©Copyright 2023 Anoop Mysore Nataraja
[3] BOOM is a RISC-V core generator written in Chisel, configurable to generate Verilog BOOM designs with varying complexity. Chisel (previous article context — BOOM/Chiffre claim)
[4] Gemmini is an open-source, Chisel-based hardware generator for matrix-multiplication accelerators developed at UC Berkeley, elaborating a RoCC-based accelerator with a non-standard RISC-V custom extension and a direct TileLink connection to the L2 cache. Design and Application of a Co-Simulation Framework for Chisel
[5] Chipyard is a chip-development framework that unifies Rocket Core and related accelerators into a single environment, in which CFC is integrated as a sub-project of the verification repository. Design and Application of a Co-Simulation Framework for Chisel
[6] ChiselTest is a library that supports creating test-harness capabilities for Chisel-based designs, enabling clock stepping and wire poking/peeking, and rebuilds a simulation binary for every test run. Design and Application of a Co-Simulation Framework for Chisel
[7] CFC is an instruction-accurate co-simulation framework for Chisel that pairs a functional Rocket Chip-based core model with an RTL simulation of a RoCC accelerator, with simulator-binary caching that reuses binaries when the underlying Chisel code has not changed. Design and Application of a Co-Simulation Framework for Chisel
[8] Chiffre and PORTRUSH operate on Chisel designs via the FIRRTL compiler, using a custom FIRRTL pass compiled with sbt to analyze and instrument hardware; the described Chiffre experiment was limited to the BOOM core because Chiffre only supported Chisel descriptions. PORTRUSH: Detect Write Port Contention
[9] UnityChipForXiangShan performs unit testing on the Kunminghu architecture of the XiangShan Processor using Python as the primary verification language and lists learning Chisel as a project objective. UnityChip For XiangShan Processor
[10] The ARMChisel processor model, built with Chisel for ARM V4 ISA compatibility, is verified through four Chisel-tailored stages: Chisel-level primary verification, rapid coverage verification, direct test verification, and complex-application verification, with FPGA-accelerated verification of large applications. Research on functional verification method processor model built by Chisel
[11] jpillora/chisel is a Go-based project described as 'a fast TCP/UDP tunnel over HTTP,' distinct from the Chisel hardware construction language. jpillora/chisel — A fast TCP/UDP tunnel over HTTP