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Chisel

Tool WIKI v2 · 8/11/2026

Chisel is a hardware description/construction language embedded in Scala, used to generate RTL (Verilog) for RISC-V processors and accelerators. It powers open-source projects including BOOM, Rocket Chip, Gemmini, and the XiangShan Kunminghu architecture, and is the hardware-description language targeted by the UnityChipForXiangShan verification framework. The name 'Chisel' is also used by an unrelated Go-based TCP/UDP tunneling tool (jpillora/chisel).

Overview

The name Chisel appears in two distinct contexts in the provided evidence:

  1. Chisel hardware construction language — an HDL embedded in Scala, used to generate Verilog for RISC-V cores, accelerators, and other digital designs. This is the dominant and most relevant meaning given the related entities and supporting evidence.
  2. jpillora/chisel — a separate Go-based tool described as "a fast TCP/UDP tunnel over HTTP," not connected to the hardware-construction language by the supplied evidence.

The two uses of the name should be treated as distinct projects.

Chisel as a hardware construction language

Chisel is an HDL embedded into the Scala programming language. A key advantage of embedding hardware description in Scala is that Scala-based software elements can interact with Chisel-based hardware elements without the need for a DPI-type connection. For example, a Scala object can read data from an input stream, perform a software function on that data, and then poke the result into the I/O of a Chisel-based hardware module.

Chisel is grouped with other higher-level hardware-description approaches such as TL Verilog and Bluespec that raise the abstraction level at which designers describe hardware, which in turn raises the abstraction level of verification. Chisel designs typically compile through the FIRRTL intermediate representation, which can then be further elaborated into Verilog for simulation, FPGA prototyping, or ASIC implementation.

Chisel in RISC-V and accelerator ecosystems

Chisel is the primary HDL used across several UC Berkeley-origin open-source RISC-V projects:

  • BOOM — a configurable, speculative out-of-order RISC-V core generator written in Chisel, which can elaborate Verilog BOOM designs with varying complexity.
  • Rocket Chip / Rocket Core — Chisel-based generator infrastructure forming part of the Chipyard chip-development framework that unifies Rocket Core and related accelerators into a single environment.
  • Gemmini — an open-source, Chisel-based hardware generator for systolic-array matrix-multiplication accelerators developed at UC Berkeley; for a given configuration it elaborates a RoCC-based accelerator that is controlled through a non-standard RISC-V custom extension and interfaces with memory through a direct TileLink connection to the L2 cache.
  • XiangShan / Kunminghu — the open-source XiangShan processor (Kunminghu architecture) whose RTL is written in Chisel, and which is the design under test in the UnityChipForXiangShan unit-testing project.

These projects illustrate Chisel's role both as a design language and as a verification target, since many of the tools built around them (ChiselTest, PORTRUSH, Chiffre, UnityChipForXiangShan) operate directly on Chisel/FIRRTL sources.

Chisel in verification and tooling

ChiselTest

ChiselTest is a library that supports the creation of test-harness capabilities for Chisel-based hardware designs. These harnesses add the ability to step a design's clock while poking data into wires or peeking at the values on wires. ChiselTest forms the backbone of drivers and monitors from the chisel verification repository used in higher-level frameworks such as CFC. The ChiselTest paradigm rebuilds a simulation binary for every test run.

Co-Simulation Framework for Chisel (CFC)

CFC is an instruction-accurate co-simulation framework for Chisel designed to accelerate the verification of tightly coupled accelerators by pairing a functional model of a Rocket Chip-based core with an RTL simulation of an accelerator under test. CFC implements tools and utilities to elaborate and simulate RoCC accelerators removed from full-SoC context, along with utilities to convert hardware bundles to and from protocol buffers. When orchestrated by CFC's manager object, the functional core and the RTL accelerator form a coherent model of a full SoC, allowing SoC-level workloads to be run at RTL fidelity on an accelerator without the overhead of simulating the rest of the SoC at RTL accuracy.

CFC introduces simulator-binary caching: an existing simulation binary can be reused if the underlying Chisel code has not changed between test runs, in contrast to ChiselTest, which rebuilds for every run. The components of CFC that interact with HDL devices are designed entirely in Scala and Chisel, so co-simulation can be run from within sbt without having to elaborate a Chisel design into Verilog and port it into an external framework.

Chiffre and PORTRUSH-style instrumentation

Tools such as Chiffre and PORTRUSH operate on hardware designs written in Chisel by leveraging the FIRRTL compiler infrastructure. They use a custom FIRRTL pass — built with sbt — to compile Chisel source into an intermediate FIRRTL representation for static analysis and then further compile FIRRTL into Verilog. At the time of the described Chiffre experiment, the tool could only work with hardware descriptions written in Chisel, which limited its automatic congestor-insertion experiment to the BOOM core.

UnityChipForXiangShan

The UnityChipForXiangShan project performs unit testing on the Kunminghu architecture of the XiangShan Processor through open-source crowdsourcing, using Python as the primary verification language. As part of its learning objectives, the project instructs contributors to learn the Chisel hardware description language, study related code and papers, and master current CPU-architectural design concepts. The project's workflow downloads RTL code, compiles all available modules to be verified, and runs Python-based test cases against the elaborated Chisel designs.

Functional verification using Chisel (ARM Chisel case study)

Reported work on an ARM V4-compatible processor model named "ARMChisel" describes a Chisel-built processor as a high-complexity hardware design and applies four verification stages tailored to the Chisel language: (1) primary verification at the Chisel level, (2) rapid coverage verification, (3) direct test verification, and (4) verification of complex applications. Testbenches are constructed in both the Chisel environment and the Verilog environment to find and localize errors quickly while collecting coverage, with FPGA acceleration used to speed up large-application verification.

Disambiguation

The provided evidence does not link the Go TCP/UDP tunneling project jpillora/chisel with the Chisel hardware construction language; they should be treated as distinct projects sharing a name. The relationship between the two is not established by any chunk in the current evidence.

Public GitHub context

The public GitHub metadata supplied for jpillora/chisel identifies a separate project: a Go repository titled jpillora/chisel, summarized as "A fast TCP/UDP tunnel over HTTP," with 16,375 stars and 1,607 forks as of the supplied update timestamp.

LINKED ENTITIES

1 links
UnityChipForXiangShan USES

CITATIONS

11 sources
11 citations
[1] Chisel is an HDL embedded into the Scala programming language, allowing Scala software elements to interact with Chisel hardware elements without a DPI-type connection. Design and Application of a Co-Simulation Framework for Chisel
[2] Chisel groups with TL Verilog and Bluespec as a higher-level hardware-description DSL that raises the abstraction level of both design and verification. ©Copyright 2023 Anoop Mysore Nataraja
[3] BOOM is a RISC-V core generator written in Chisel, configurable to generate Verilog BOOM designs with varying complexity. Chisel (previous article context — BOOM/Chiffre claim)
[4] Gemmini is an open-source, Chisel-based hardware generator for matrix-multiplication accelerators developed at UC Berkeley, elaborating a RoCC-based accelerator with a non-standard RISC-V custom extension and a direct TileLink connection to the L2 cache. Design and Application of a Co-Simulation Framework for Chisel
[5] Chipyard is a chip-development framework that unifies Rocket Core and related accelerators into a single environment, in which CFC is integrated as a sub-project of the verification repository. Design and Application of a Co-Simulation Framework for Chisel
[6] ChiselTest is a library that supports creating test-harness capabilities for Chisel-based designs, enabling clock stepping and wire poking/peeking, and rebuilds a simulation binary for every test run. Design and Application of a Co-Simulation Framework for Chisel
[7] CFC is an instruction-accurate co-simulation framework for Chisel that pairs a functional Rocket Chip-based core model with an RTL simulation of a RoCC accelerator, with simulator-binary caching that reuses binaries when the underlying Chisel code has not changed. Design and Application of a Co-Simulation Framework for Chisel
[8] Chiffre and PORTRUSH operate on Chisel designs via the FIRRTL compiler, using a custom FIRRTL pass compiled with sbt to analyze and instrument hardware; the described Chiffre experiment was limited to the BOOM core because Chiffre only supported Chisel descriptions. PORTRUSH: Detect Write Port Contention
[9] UnityChipForXiangShan performs unit testing on the Kunminghu architecture of the XiangShan Processor using Python as the primary verification language and lists learning Chisel as a project objective. UnityChip For XiangShan Processor
[10] The ARMChisel processor model, built with Chisel for ARM V4 ISA compatibility, is verified through four Chisel-tailored stages: Chisel-level primary verification, rapid coverage verification, direct test verification, and complex-application verification, with FPGA-accelerated verification of large applications. Research on functional verification method processor model built by Chisel
[11] jpillora/chisel is a Go-based project described as 'a fast TCP/UDP tunnel over HTTP,' distinct from the Chisel hardware construction language. jpillora/chisel — A fast TCP/UDP tunnel over HTTP

VERSION HISTORY

v2 · 8/11/2026 · minimax/minimax-m3 (current)
v1 · 5/27/2026 · gpt-5.5