Direct Test Verification

Technique

Direct Test Verification is one of four verification stages designed for an ARM V4 ISA-compatible Chisel-based processor model (ARMChisel). It sits alongside Chisel-level primary verification, rapid coverage verification, and complex application verification, and is applied within testbenches built in both the Chisel and Verilog environments to locate and isolate design errors while collecting coverage.

First seen 8/6/2026

Last seen 8/6/2026

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Overview

Direct Test Verification is a verification technique/strategy used in the functional verification of a Chisel-built ARM V4 instruction set architecture (ISA) processor model named ARMChisel. It is described in the paper "Research on functional verification method processor model built by Chisel" by Lening Wu, Miao Wang, and Fu Chen (Journal of Northwestern Polytechnical University, 2023, 41(5): 1024–1032).

Context: The Four-Stage Verification Strategy

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Research on functional verification method processor model built by Chisel ← uses 100% 1e

The paper employs direct test verification as one of its verification stages.

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CITATIONS

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[1] Direct Test Verification is one of four verification stages designed for the ARMChisel processor model. Research on functional verification method processor model built by Chisel

[2] The four stages are: Chisel-level primary verification, rapid coverage verification, direct test verification, and complex application verification. Research on functional verification method processor model built by Chisel

[3] The testbenches are built in both the Chisel and Verilog environments and collect coverage while quickly and accurately finding and locating errors. Research on functional verification method processor model built by Chisel

[4] FPGA acceleration is used to speed up verification of large-scale application programs and shorten the verification cycle. Research on functional verification method processor model built by Chisel

[5] A random instruction generator supporting all instructions of the ARM V4 ISA architecture is designed to speed up test stimulus generation. Research on functional verification method processor model built by Chisel