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Direct Test Verification

Technique WIKI v1 · 8/6/2026

Direct Test Verification is one of four verification stages designed for an ARM V4 ISA-compatible Chisel-based processor model (ARMChisel). It sits alongside Chisel-level primary verification, rapid coverage verification, and complex application verification, and is applied within testbenches built in both the Chisel and Verilog environments to locate and isolate design errors while collecting coverage.

Overview

Direct Test Verification is a verification technique/strategy used in the functional verification of a Chisel-built ARM V4 instruction set architecture (ISA) processor model named ARMChisel. It is described in the paper "Research on functional verification method processor model built by Chisel" by Lening Wu, Miao Wang, and Fu Chen (Journal of Northwestern Polytechnical University, 2023, 41(5): 1024–1032).

Context: The Four-Stage Verification Strategy

According to the paper, the verification of the ARMChisel processor model is organized into four stages, tailored to the characteristics of the Chisel hardware construction language:

  1. Primary verification at the Chisel level — initial sanity checks performed directly in the Chisel environment.
  2. Rapid coverage verification — fast iteration to drive coverage forward.
  3. Direct test verification — targeted, hand-crafted or directed test cases used to pinpoint and localize specific design errors.
  4. Verification of complex applications — large-scale application-level workloads, accelerated on FPGA to shorten the verification cycle.

The four-stage strategy is intended to ensure that the expected coverage targets are reached while keeping the overall design and verification cycle short.

Role of Direct Test Verification

Direct Test Verification occupies the third stage of this strategy. It is applied after rapid coverage verification has been used to exercise the design broadly, and before complex application verification. Its purpose is to:

  • Run targeted/directed tests against the processor model to expose specific bugs that random stimuli may not efficiently surface.
  • Enable quick and accurate error detection and error localization while coverage is being collected.
  • Complement the random instruction generator (which supports the full ARM V4 ISA) by providing focused stimuli for known corner cases or suspected problem areas.

Testbench Environment

Direct Test Verification is executed within testbenches built in two environments:

  • The Chisel environment, supporting early-stage and Chisel-native verification.
  • The Verilog environment, supporting verification once the Chisel design has been emitted to Verilog for downstream tooling and FPGA acceleration.

These testbenches collect coverage and report/locate errors in tandem, which is what allows the direct test stage to contribute to both error discovery and coverage closure.

Relationship to Other Stages

Stage Purpose Stimulus type
Chisel-level primary verification Sanity check the Chisel model Trivial / smoke
Rapid coverage verification Drive coverage quickly Broad random
Direct test verification Pinpoint and localize errors Directed / hand-crafted
Complex application verification Validate realistic workloads, FPGA-accelerated Real applications

Summary

Direct Test Verification is a directed-test stage in a four-stage functional verification flow for an ARM V4 Chisel processor model. Combined with random instruction generation and FPGA-accelerated application-level verification, it helps the testbench quickly find and localize design errors while collecting coverage, shortening the overall verification cycle.

Cited Paper

LINKED ENTITIES

1 links
Research on functional verification method processor model built by Chisel USES

CITATIONS

5 sources
5 citations
[1] Direct Test Verification is one of four verification stages designed for the ARMChisel processor model. Research on functional verification method processor model built by Chisel
[2] The four stages are: Chisel-level primary verification, rapid coverage verification, direct test verification, and complex application verification. Research on functional verification method processor model built by Chisel
[3] The testbenches are built in both the Chisel and Verilog environments and collect coverage while quickly and accurately finding and locating errors. Research on functional verification method processor model built by Chisel
[4] FPGA acceleration is used to speed up verification of large-scale application programs and shorten the verification cycle. Research on functional verification method processor model built by Chisel
[5] A random instruction generator supporting all instructions of the ARM V4 ISA architecture is designed to speed up test stimulus generation. Research on functional verification method processor model built by Chisel