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RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption

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First seen 9/29/2026

Last seen 9/29/2026

Evidence 1 chunks

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NEIGHBORHOOD

6 nodes · 9 edges

graph · RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption · depth=1

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RELATIONSHIPS

7 connections

RISE introduces → 98% 1e evidence

Authors present a new RISC-V SoC named RISE for HE en/decryption acceleration on the edge.

Error sampling evaluates → 92% 1e evidence

Profiling of edge-side conversion operations highlights error sampling as a bottleneck.

RTL uses → 96% 1e evidence

A complete RTL model is used to conduct the evaluation of RISE.

RISE evaluates → 96% 1e evidence

Experimental evaluation is performed on RISE using its RTL implementation.

RISC-V processor ← compares with 93% 1e evidence

Energy efficiency of RISE is compared to a standalone RISC-V processor baseline.

Number Theoretic Transform evaluates → 88% 1e evidence

Authors identify NTT as the key bottleneck and target it with data-level parallelism.

RISC-V processor evaluates → 85% 1e evidence

Baseline performance/energy using just the RISC-V processor is evaluated for comparison with RISE.