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RISE

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First seen 9/29/2026

Last seen 9/29/2026

Evidence 1 chunks

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NEIGHBORHOOD

11 nodes · 12 edges

graph · RISE · depth=1

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RELATIONSHIPS

11 connections

RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption ← introduces 98% 1e evidence

Authors present a new RISC-V SoC named RISE for HE en/decryption acceleration on the edge.

RISC-V targets ISA → 90% 1e evidence

RISE is a RISC-V-based SoC, indicating it targets the RISC-V instruction set.

Pseudo-random number generator core uses → 98% 1e evidence

A lightweight PRNG core is leveraged as part of RISE to accelerate operations.

Fast sampling techniques uses → 96% 1e evidence

Fast sampling is combined with the PRNG core to accelerate error sampling.

Number Theoretic Transform implements → 95% 1e evidence

NTT is implemented within RISE to accelerate encryption and decryption.

Data-level parallelism uses → 95% 1e evidence

Data-level parallelism is employed to implement the NTT operation efficiently.

Unified en/decryption datapath implements → 95% 1e evidence

A single datapath is used for both encryption and decryption to save area.

Memory reuse uses → 90% 1e evidence

Memory reuse is exploited to reduce resource usage.

Data reordering uses → 90% 1e evidence

Data reordering is used to help minimize memory footprint and improve efficiency.

On-chip memory uses → 80% 1e evidence

Architectural techniques are applied so that the design utilizes minimal on-chip memory.

RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption ← evaluates 96% 1e evidence

Experimental evaluation is performed on RISE using its RTL implementation.