Constrained Random Test Environment for SoC Verification using VERA

Paper

First seen 7/16/2026

Last seen 7/16/2026

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Besyakov, V. authored by → 100% 1e

Besyakov, V. is listed as a co-author of the paper on constrained random test environment using VERA.

Shleifman, D. authored by → 100% 1e

Shleifman, D. is listed as a co-author of the paper on constrained random test environment using VERA.

Vera uses → 100% 1e

The paper describes a constrained random test environment using the VERA tool.

SoC Verification uses → 100% 1e

The paper addresses SoC Verification using constrained random test generation with VERA.