00

VerilogEval: evaluating large language models for Verilog code generation

Paper ☆ WATCH ⎘ SHARE

First seen 9/3/2026

Last seen 9/3/2026

Evidence 1 chunks

01

NEIGHBORHOOD

5 nodes · 7 edges

graph · VerilogEval: evaluating large language models for Verilog code generation · depth=1

02

RELATIONSHIPS

4 connections

Brucek Khailany authored by → 100% 1e evidence

VerilogEval lists Brucek Khailany as a co-author.

Haoxing Ren authored by → 100% 1e evidence

VerilogEval lists Haoxing Ren as a co-author.

GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation ← mentions 90% 1e evidence

The paper cites VerilogEval as a benchmark for RTL code generation.

Nathaniel Pinckney authored by → 100% 1e evidence

VerilogEval is authored by M. Liu, N. Pinckney, B. Khailany, and H. Ren.