Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

Paper

A 2025 TU Wien work by Johannes Zottele, Matthias Raschhofer, Benedikt Huber, and Andreas Krall describing automatic generation of QEMU instruction-set-simulator frontends from OpenVADL/VADL processor descriptions by lowering the VIAM intermediate representation to QEMU TCG operations. The slides report evaluation on Embench for RISC-V 64 IM and AArch64, with generated frontends achieving up to 44% lower runtime than upstream QEMU.

First seen 5/29/2026

Last seen 5/29/2026

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Overview

Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL is a 2025 work presented by Johannes Zottele, Matthias Raschhofer, Benedikt Huber, and Andreas Krall at Technische Universität Wien. The slide deck is dated June 30, 2025 and focuses on generating QEMU-based instruction set simulator frontends from processor descriptions written in OpenVADL/VADL. [1]

Technical approach

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RELATIONSHIPS

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Johannes Zottele authored by → 100% 1e

The paper is authored by Johannes Zottele.

Matthias Raschhofer authored by → 100% 1e

The paper is authored by Matthias Raschhofer.

Benedikt Huber authored by → 100% 1e

The paper is authored by Benedikt Huber.

Andreas Krall authored by → 100% 1e

The paper is authored by Andreas Krall.

Technische Universität Wien published by → 100% 1e

The paper is published by Technische Universität Wien.

QEMU introduces → 90% 1e

The paper introduces the approach of generating a QEMU-based ISS from an OpenVADL processor description.

OpenVADL uses → 100% 1e

The paper describes using OpenVADL as the processor description framework to generate QEMU simulators.

RISC-V evaluates → 95% 1e

The paper evaluates a RISC-V 64 (IM) implementation using Embench benchmarks.

Embench evaluates → 95% 1e

The paper uses Embench as an evaluation benchmark suite.

LINKED ENTITIES

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Johannes Zottele AUTHORED_BY Extracted graph relationship

Matthias Raschhofer AUTHORED_BY Extracted graph relationship

Benedikt Huber AUTHORED_BY Extracted graph relationship

Andreas Krall AUTHORED_BY Extracted graph relationship

Technische Universität Wien PUBLISHED_BY Extracted graph relationship

QEMU INTRODUCES Extracted graph relationship

OpenVADL USES Extracted graph relationship

RISC-V EVALUATES Extracted graph relationship

Embench EVALUATES Extracted graph relationship

CITATIONS

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[1] The work is titled 'Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL', is dated June 30, 2025, and lists Johannes Zottele, Matthias Raschhofer, Benedikt Huber, and Andreas Krall at Technische Universität Wien. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[2] OpenVADL/VADL specifications feed a frontend and VIAM architecture-synthesis stage, with generated artifacts including a QEMU simulator. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[3] The QEMU generation approach lowers VIAM through TCG-oriented operations into generated C code for a QEMU frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[4] The slides demonstrate the approach with a RISC-V 64 ADDI instruction and show generated C code using QEMU TCG operations such as tcg_gen_add_i64 and tcg_gen_mov_i64. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[5] The evaluation uses Embench workloads for RISC-V 64 IM and AArch64, reporting relative runtime against QEMU. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[6] The conclusion states that generated frontends achieved up to 44% lower runtime than upstream and lists future work including TCG vector support, user-mode simulation, floating-point support, and a cycle-approximate simulator based on the ISS. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL