Matthias Raschhofer
PersonMatthias Raschhofer is listed as a co-author of the 2025 work "Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL," associated with Technische Universität Wien, Vienna, Austria.
First seen 5/29/2026
Last seen 5/29/2026
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Matthias Raschhofer is listed as one of the authors of "Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL", alongside Johannes Zottele, Benedikt Huber, and Andreas Krall. The slide deck for the work is dated June 30, 2025, and identifies the author group with Technische Universität Wien, Vienna, Austria.
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1 connections Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL ← authored by 100% 1e
The paper is authored by Matthias Raschhofer.
CITATIONS
5 sources5 citations — click to expand
[1] Matthias Raschhofer is listed as a co-author of "Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL." Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[2] The slide deck is dated June 30, 2025 and identifies the author group with Technische Universität Wien, Vienna, Austria. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[3] The work describes automatic generation of QEMU frontends from VADL/OpenVADL processor specifications. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[4] The described generation approach lowers VIAM to QEMU TCG operations and emits generated C code for QEMU translation functions. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[5] The evaluation compares generated QEMU frontends on Embench workloads for RISC-V 64 and AArch64, and the conclusion reports up to 44% lower runtime than upstream. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL