Overview

Matthias Raschhofer is listed as one of the authors of "Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL", alongside Johannes Zottele, Benedikt Huber, and Andreas Krall. The slide deck for the work is dated June 30, 2025, and identifies the author group with Technische Universität Wien, Vienna, Austria.

Associated work

Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

The cited work presents an approach for automatically generating QEMU frontends from processor descriptions written in the Vienna Architecture Description Language / OpenVADL toolchain. The slides describe a flow from a VADL specification through the VADL frontend and VIAM architecture synthesis, with QEMU simulator generation as one of the resulting targets.

The technical approach described in the slides lowers the VADL Intermediate Architecture Model (VIAM) to QEMU TCG operations and then emits C code for QEMU translation functions. The example shown for RISC-V 64 ADDI demonstrates generated TCG-based C code that reads source registers and immediates, performs a tcg_gen_add_i64, and writes the result.

The evaluation slides compare generated QEMU frontends against upstream QEMU on Embench workloads for RISC-V 64 and AArch64. The conclusion states that OpenVADL enables automatic generation of QEMU frontends from VADL specifications and reports up to 44% lower runtime than upstream in the presented evaluation.