Technische Universität Wien

Organization

Technische Universität Wien is identified in the provided evidence as an institution in Vienna, Austria, associated with the 2025 work “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL.” The slide deck credits Johannes Zottele, Matthias Raschhofer, Benedikt Huber, and Andreas Krall, and presents OpenVADL work on automatically generating QEMU frontends from VADL processor specifications.

First seen 5/29/2026

Last seen 5/29/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Technische Universität Wien is identified in the provided evidence as being located in Vienna, Austria. The evidence is a June 30, 2025 slide deck titled Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL, which lists Johannes Zottele, Matthias Raschhofer, Benedikt Huber, and Andreas Krall together with “Technische Universität Wien, Vienna, Austria.”

Associated work in the evidence

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections

Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL ← published by 100% 1e

The paper is published by Technische Universität Wien.

LINKED ENTITIES

1 links

Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL PUBLISHED_BY Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Technische Universität Wien is identified in the evidence as being in Vienna, Austria. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[2] The June 30, 2025 slide deck is titled “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL” and lists Johannes Zottele, Matthias Raschhofer, Benedikt Huber, and Andreas Krall. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[3] The slide deck describes OpenVADL as enabling automatic generation of QEMU frontends from VADL specifications by lowering VIAM to TCG operations and generating C code. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[4] The evidence describes QEMU as an open-source machine emulator using dynamic binary translation and the architecture-agnostic TCG intermediate representation. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[5] The slide deck reports that the generated frontend achieved up to 44% lower runtime than upstream and lists future work including TCG vector support, user-mode simulation, floating-point support, and a cycle-approximate simulator based on the ISS. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL