Overview

Technische Universität Wien is identified in the provided evidence as being located in Vienna, Austria. The evidence is a June 30, 2025 slide deck titled Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL, which lists Johannes Zottele, Matthias Raschhofer, Benedikt Huber, and Andreas Krall together with “Technische Universität Wien, Vienna, Austria.”

Associated work in the evidence

The provided slide deck presents work on generating a QEMU-based instruction set simulator from a processor description written in OpenVADL. It describes OpenVADL as using a VADL specification, a frontend, and a VIAM architecture synthesis flow, with outputs including a QEMU simulator and other tooling.

The slides summarize QEMU as an open-source machine emulator using dynamic binary translation and an architecture-agnostic intermediate representation called TCG. The generation flow shown in the evidence lowers the VADL Intermediate Architecture Model (VIAM) to TCG operations and generates C code for a QEMU frontend.

Reported results and future work

The slide deck reports evaluation results for RISC-V 64 IM and AArch64 Embench workloads relative to QEMU, and concludes that OpenVADL enables automatic generation of QEMU frontends from VADL specifications. The conclusion states that the generated frontend achieved up to 44% lower runtime than upstream. Future work listed in the evidence includes TCG vector support for tensor instructions, user-mode simulation, floating-point instruction support, and a cycle-approximate simulator based on the instruction set simulator.