Andreas Krall
PersonAndreas Krall is listed as a co-author of the 2025 slide deck “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL,” affiliated in that document with Technische Universität Wien, Vienna, Austria.
First seen 5/29/2026
Last seen 5/29/2026
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Overview
Andreas Krall is named as one of the authors of the slide deck “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL.” The document lists the authors as Johannes Zottele, Matthias Raschhofer, Benedikt Huber, and Andreas Krall, and gives the date as June 30, 2025, with Technische Universität Wien, Vienna, Austria shown on the title slide.
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1 connections Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL ← authored by 100% 1e
The paper is authored by Andreas Krall.
CITATIONS
6 sources6 citations — click to expand
[1] Andreas Krall is listed as a co-author of “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL.” Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[2] The slide deck is dated June 30, 2025 and identifies Technische Universität Wien, Vienna, Austria on the title slide. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[3] The presentation describes an OpenVADL flow from a VADL specification through frontend and VIAM architecture synthesis to outputs including a QEMU simulator, hardware, and a cycle-approximate simulator. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[4] The presentation characterizes QEMU as an open-source machine emulator using dynamic binary translation and an architecture-agnostic IR called TCG. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[5] The cited work’s conclusion states that OpenVADL enables automatic generation of QEMU frontends from VADL specifications by lowering VIAM to TCG operations. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[6] The cited work reports that the generated frontend achieved up to 44% lower runtime than upstream in its evaluation. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL