Overview

Andreas Krall is named as one of the authors of the slide deck “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL.” The document lists the authors as Johannes Zottele, Matthias Raschhofer, Benedikt Huber, and Andreas Krall, and gives the date as June 30, 2025, with Technische Universität Wien, Vienna, Austria shown on the title slide.

Associated work

In the cited OpenVADL/QEMU slide deck, Krall is associated with work on generating a QEMU-based instruction set simulator from a processor description written in OpenVADL. The presentation describes an OpenVADL flow in which a VADL specification is processed through a frontend and VIAM architecture synthesis, with outputs including a QEMU simulator, hardware, and a cycle-approximate simulator.

The presentation states that QEMU is an open-source machine emulator using dynamic binary translation and an architecture-agnostic intermediate representation, TCG. It presents a generation approach that lowers the VADL Intermediate Architecture Model (VIAM) to TCG operations and then generates C code for a QEMU frontend.

Reported results in the cited work

The slide deck reports evaluation results for generated QEMU frontends on RISC-V 64 (IM) and AArch64 Embench benchmarks. Its conclusion states that OpenVADL enables automatic generation of QEMU frontends from VADL specifications, that this is achieved by lowering VIAM to TCG operations, and that the generated frontend achieved up to 44% lower runtime than upstream in the reported evaluation.