Johannes Zottele

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Johannes Zottele is listed as an author of the 2025 OpenVADL slide deck/paper “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL,” presented with co-authors Matthias Raschhofer, Benedikt Huber, and Andreas Krall at Technische Universität Wien.

First seen 5/29/2026

Last seen 5/29/2026

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Johannes Zottele is listed as an author of “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL”, dated June 30, 2025. The same title slide lists Matthias Raschhofer, Benedikt Huber, and Andreas Krall as co-authors and identifies Technische Universität Wien, Vienna, Austria.

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Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL ← authored by 100% 1e

The paper is authored by Johannes Zottele.

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[1] Johannes Zottele is listed as an author of “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL,” dated June 30, 2025, with Matthias Raschhofer, Benedikt Huber, and Andreas Krall, and the title slide identifies Technische Universität Wien, Vienna, Austria. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[2] The OpenVADL work presents generation of a QEMU-based instruction set simulator from a processor description, using VIAM lowering to TCG operations and C-code generation for a QEMU frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[3] The slides show a RISC-V 64 ADDI example across VIAM, lowered VIAM, and generated C code using QEMU TCG operations. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[4] The reported evaluation uses Embench for RISC-V 64 (IM) and AArch64 and concludes that the generated frontend achieved up to 44% lower runtime than upstream. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL