Overview

Johannes Zottele is listed as an author of “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL”, dated June 30, 2025. The same title slide lists Matthias Raschhofer, Benedikt Huber, and Andreas Krall as co-authors and identifies Technische Universität Wien, Vienna, Austria.

Associated work

The cited OpenVADL work describes generating a QEMU-based instruction set simulator from a processor description written in OpenVADL/VADL. The presented workflow lowers the VADL Intermediate Architecture Model (VIAM) to QEMU TCG operations and generates C code for a QEMU frontend. The slides include an example for RISC-V 64 ADDI, showing VIAM, lowered VIAM, and generated TCG translation code.

Reported evaluation context

The presentation evaluates generated QEMU frontends using Embench for RISC-V 64 (IM) and AArch64. Its conclusion states that OpenVADL can automatically generate QEMU frontends from VADL specifications, that this is achieved by lowering VIAM to TCG operations, and that the generated frontend achieved up to 44% lower runtime than upstream in the reported evaluation.