Overview

Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL is a 2025 work presented by Johannes Zottele, Matthias Raschhofer, Benedikt Huber, and Andreas Krall at Technische Universität Wien. The slide deck is dated June 30, 2025 and focuses on generating QEMU-based instruction set simulator frontends from processor descriptions written in OpenVADL/VADL. [1]

Technical approach

The work positions OpenVADL as a processor-description environment whose VADL specifications feed a frontend and a VIAM architecture-synthesis stage. In the shown OpenVADL overview, generated outputs include assembler/linker support, compiler support, a cycle-approximate simulator, hardware, and a QEMU simulator. [1]

The QEMU-related generation flow consists of decoder generation and transformation from the VADL Intermediate Architecture Model (VIAM) to QEMU's Tiny Code Generator (TCG) operations. The pipeline shown in the slides is: VIAM transformation, lowered VIAM, C-code generation, and integration as a QEMU frontend that executes guest programs on the QEMU system. [1]

Example: RISC-V ADDI

The slides illustrate the approach using a RISC-V 64 ADDI instruction specified in VADL. The VADL example defines an instruction-set architecture RV64I, a register file X, an instruction format Itype, and the instruction behavior:

X(rd) := X(rs1) + immS

The same instruction is shown as a VIAM graph with field accesses, register reads and writes, and an add operation. It is then lowered to TCG-oriented operations such as tcg_add and tcg_mov, and finally emitted as C code for a QEMU translation function trans_addi. The generated C code obtains the destination and source register values, creates a constant for the immediate, emits tcg_gen_add_i64, and then emits tcg_gen_mov_i64. [1]

Evaluation

The evaluation shown in the slides compares generated QEMU frontends against upstream QEMU using Embench workloads. Two benchmark plots are included: one for RISC-V 64 (IM) Embench and one for AArch64 Embench, both reporting relative runtime where lower is better. The conclusion states that the generated frontend achieves up to 44% lower runtime than upstream. [1]

Conclusion and future work

The slide conclusion states that OpenVADL enables automatic generation of QEMU frontends from VADL specifications by lowering VIAM to TCG operations. Listed future work includes TCG vector support for tensor instructions, user-mode simulation, floating-point instruction support, and a cycle-approximate simulator based on the instruction set simulator. [1]