OpenVADL — STIMSMITH

OpenVADL

Tool

OpenVADL is a VADL-based tool for generating architecture tooling, including QEMU instruction-set-simulator frontends. Its documented QEMU-generation flow starts from a VADL specification, builds a VIAM intermediate architecture model, performs decoder generation and TCG transformation, lowers VIAM to TCG operations, and emits C code for a QEMU frontend.

First seen 5/29/2026

Last seen 5/29/2026

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Wiki v1

WIKI

Overview

OpenVADL is presented as a toolchain around the Vienna Architecture Description Language (VADL). A VADL specification is processed by a frontend and architecture-synthesis stage into the VADL Intermediate Architecture Model (VIAM), with generated outputs shown for an assembler/linker, compiler, QEMU simulator, hardware, and a cycle-approximate simulator. [OpenVADL overview]

The 2025 presentation Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL states that OpenVADL enables automatic generation of QEMU frontends from VADL specifications. [Automatic QEMU frontend generation]

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NEIGHBORHOOD

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RELATIONSHIPS

8 connections

Vienna Architecture Description Language (VADL) uses → 100% 1e

OpenVADL uses the Vienna Architecture Description Language as its specification input.

Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL ← uses 100% 1e

The paper describes using OpenVADL as the processor description framework to generate QEMU simulators.

VADL Intermediate Architecture Model (VIAM) introduces → 95% 1e

OpenVADL introduces and uses the VADL Intermediate Architecture Model (VIAM) as part of its compilation pipeline.

Cycle-Approximate Simulator introduces → 90% 1e

OpenVADL generates a cycle-approximate simulator as one of its outputs.

Decoder Generation uses → 95% 1e

OpenVADL's QEMU generation pipeline includes a decoder generation step.

TCG Transformation uses → 95% 1e

OpenVADL applies a TCG transformation step to VIAM during QEMU code generation.

RISC-V evaluates → 90% 1e

OpenVADL generates and evaluates a RISC-V 64 simulator.

C-Code Generation uses → 95% 1e

OpenVADL generates C code as the final step before producing a QEMU frontend.

LINKED ENTITIES

8 links

Vienna Architecture Description Language (VADL) USES Extracted graph relationship

VADL Intermediate Architecture Model (VIAM) INTRODUCES Extracted graph relationship

Cycle-Approximate Simulator INTRODUCES Extracted graph relationship

Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL USES Extracted graph relationship

Decoder Generation USES Extracted graph relationship

TCG Transformation USES Extracted graph relationship

C-Code Generation USES Extracted graph relationship

RISC-V EVALUATES Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] OpenVADL overview Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[2] Automatic QEMU frontend generation Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[3] QEMU generation pipeline Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[4] VIAM ADDI representation Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[5] Lowered VIAM and generated C Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[6] Evaluation results Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[7] Future work Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL