C-Code Generation

Technique

C-Code Generation is the OpenVADL QEMU-generation stage that emits C translation functions for a QEMU frontend from a Lowered VIAM representation of instructions.

First seen 5/29/2026

Last seen 5/29/2026

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Overview

C-Code Generation is a stage in the OpenVADL flow for generating a QEMU-based instruction set simulator from a VADL processor description. In the QEMU generation pipeline, the flow proceeds from VIAM through a TCG transformation into Lowered VIAM, then through C-Code Generation into a generated QEMU frontend.

Role in the OpenVADL QEMU flow

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NEIGHBORHOOD

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RELATIONSHIPS

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trans_addi TCG Translation Function introduces → 90% 1e

The C-code generation step produces the trans_addi TCG translation function as output.

OpenVADL ← uses 95% 1e

OpenVADL generates C code as the final step before producing a QEMU frontend.

Lowered VIAM depends on → 95% 1e

C-code generation takes lowered VIAM as input in the OpenVADL pipeline.

LINKED ENTITIES

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OpenVADL USES Extracted graph relationship

Lowered VIAM DEPENDS_ON Extracted graph relationship

trans_addi TCG Translation Function INTRODUCES Extracted graph relationship

CITATIONS

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5 citations — click to expand

[1] C-Code Generation is a stage in the OpenVADL QEMU generation pipeline, following Lowered VIAM and producing a QEMU frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[2] QEMU uses dynamic binary translation and an architecture-agnostic IR called TCG. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[3] The generated RISC-V 64 ADDI C translation function is named trans_addi and emits TCG operations including tcg_gen_add_i64 and tcg_gen_mov_i64. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[4] Lowered VIAM for RISC-V 64 ADDI represents the instruction using TCG-oriented elements such as register variables, constants, temporaries, tcg_add, and tcg_mov. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[5] The OpenVADL presentation concludes that QEMU frontends can be generated automatically from VADL specifications by lowering VIAM to TCG operations and reports up to 44% lower runtime than upstream for the generated frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL