trans_addi TCG Translation Function

CodeArtifact

`trans_addi` is a generated QEMU TCG translation function for the RISC-V 64 `ADDI` instruction. In the OpenVADL example, it lowers the instruction semantics `X(rd) := X(rs1) + immS` into 64-bit TCG operations by reading the source register, materializing the sign-extended immediate as a TCG constant, emitting `tcg_gen_add_i64`, moving the result to the destination register, and returning `true`.

First seen 5/29/2026

Last seen 5/29/2026

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Overview

trans_addi is presented as generated C code for a QEMU Tiny Code Generator (TCG) translation function for the RISC-V 64 ADDI instruction. The example comes from an OpenVADL-to-QEMU generation flow in which a VADL instruction-set specification is transformed through VIAM and lowered to TCG operations before C code is emitted for a QEMU frontend. [1]

Source instruction semantics

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RELATIONSHIPS

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RISC-V implements → 100% 1e

The trans_addi TCG translation function implements the RISC-V 64 ADDI instruction.

Tiny Code Generator (TCG) uses → 100% 1e

The trans_addi function uses TCG primitives such as tcg_gen_add_i64 and tcg_gen_mov_i64.

C-Code Generation ← introduces 90% 1e

The C-code generation step produces the trans_addi TCG translation function as output.

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RISC-V IMPLEMENTS Extracted graph relationship

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CITATIONS

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[1] trans_addi is generated C code for a QEMU TCG translation function for RISC-V 64 ADDI in an OpenVADL-to-QEMU generation flow. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[2] The source ADDI semantics are X(rd) := X(rs1) + immS, with immS derived from the instruction immediate as a signed value. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[3] The generated trans_addi function creates TCG values for the destination register, source register, temporary, and immediate constant, emits tcg_gen_add_i64 and tcg_gen_mov_i64, and returns true. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[4] The generation pipeline lowers VIAM to TCG operations and then emits C code for a QEMU frontend; the lowered ADDI representation includes tcg_add and tcg_mov. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL