trans_addi TCG Translation Function Wiki

Overview

trans_addi is presented as generated C code for a QEMU Tiny Code Generator (TCG) translation function for the RISC-V 64 ADDI instruction. The example comes from an OpenVADL-to-QEMU generation flow in which a VADL instruction-set specification is transformed through VIAM and lowered to TCG operations before C code is emitted for a QEMU frontend. [1]

Source instruction semantics

The source VADL example defines an RV64I-style ADDI instruction over an I-type format. Its semantic assignment is:

instruction ADDI : Itype = X(rd) := X(rs1) + immS

The immediate field immS is derived from the instruction immediate as a signed value, and the operation writes the sum of register X(rs1) and immS to register X(rd). [2]

Generated C translation function

The generated function shown for RISC-V 64 ADDI is:

static bool trans_addi(DisasContext *ctx, arg_addi *a) {
    TCGv_i64 reg_x_rd_dest = dest_x(ctx, a->rd);
    TCGv_i64 reg_x_rs1 = get_x(ctx, a->rs1);
    TCGv_i64 tmp_n4_0 = tcg_temp_new_i64();
    TCGv_i64 const_immS_n3 = tcg_constant_i64(a->immS);

    tcg_gen_add_i64(tmp_n4_0, reg_x_rs1, const_immS_n3);
    tcg_gen_mov_i64(reg_x_rd_dest, tmp_n4_0);

    return true;
}

The function takes a QEMU translation context (DisasContext *ctx) and decoded instruction arguments (arg_addi *a). It obtains a destination TCG value for rd, reads the source register rs1, creates a temporary 64-bit TCG value, materializes the immediate as a 64-bit TCG constant, emits a 64-bit add, moves the computed result into the destination register, and reports successful translation by returning true. [3]

Relationship to the lowering pipeline

The slides describe a generation pipeline in which a VADL specification is processed into VIAM, transformed into TCG-oriented form, lowered, and then emitted as C code for a QEMU frontend. The shown lowered VIAM for RISC-V 64 ADDI contains field accesses for rs1, immS, and rd, register and constant variables, a tcg_add, a destination, and a tcg_mov, matching the generated function’s tcg_gen_add_i64 followed by tcg_gen_mov_i64. [4]

Technical significance

Within the example, trans_addi illustrates how an instruction-level semantic assignment is represented as QEMU TCG IR-emitting C code. It is specifically a RISC-V 64 ADDI translation function, and it uses QEMU’s architecture-agnostic TCG mechanism rather than directly emitting host machine code. [1]