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C-Code Generation

Technique WIKI v1 · 5/29/2026

C-Code Generation is the OpenVADL QEMU-generation stage that emits C translation functions for a QEMU frontend from a Lowered VIAM representation of instructions.

Overview

C-Code Generation is a stage in the OpenVADL flow for generating a QEMU-based instruction set simulator from a VADL processor description. In the QEMU generation pipeline, the flow proceeds from VIAM through a TCG transformation into Lowered VIAM, then through C-Code Generation into a generated QEMU frontend.

Role in the OpenVADL QEMU flow

OpenVADL’s QEMU-generation approach targets QEMU, an open-source machine emulator that uses dynamic binary translation and an architecture-agnostic intermediate representation called TCG. The generated frontend is produced by lowering the VADL Intermediate Architecture Model into TCG-oriented operations and then emitting C code for QEMU’s frontend interface.

The pipeline shown in the evidence is:

VIAM -> TCG Transformation -> Lowered VIAM -> C-Code Generation -> QEMU Frontend

This means C-Code Generation depends on the Lowered VIAM form rather than directly on the original VADL instruction description.

Generated translation functions

The generated C code is structured as QEMU TCG translation functions. For the RISC-V 64 ADDI instruction, the evidence shows a generated function named trans_addi:

static bool trans_addi(DisasContext *ctx, arg_addi *a) {
    TCGv_i64 reg_x_rd_dest = dest_x(ctx, a->rd);
    TCGv_i64 reg_x_rs1 = get_x(ctx, a->rs1);
    TCGv_i64 tmp_n4_0 = tcg_temp_new_i64();
    TCGv_i64 const_immS_n3 = tcg_constant_i64(a->immS);

    tcg_gen_add_i64(tmp_n4_0, reg_x_rs1, const_immS_n3);
    tcg_gen_mov_i64(reg_x_rd_dest, tmp_n4_0);

    return true;
}

This function obtains the destination and source register operands, creates a temporary and an immediate constant, emits a TCG add operation, moves the result to the destination register, and returns success.

Relationship to Lowered VIAM

The Lowered VIAM representation shown for RISC-V 64 ADDI contains TCG-oriented nodes such as register variables, constants, temporaries, tcg_add, and tcg_mov. C-Code Generation consumes this lowered representation and emits the corresponding QEMU C helper code using calls such as tcg_gen_add_i64 and tcg_gen_mov_i64.

Reported outcome

The cited OpenVADL presentation concludes that automatic generation of QEMU frontends from VADL specifications is achieved by lowering VIAM to TCG operations. It also reports that the generated frontend achieved up to 44% lower runtime than upstream in the presented evaluation.

CITATIONS

5 sources
5 citations
[1] C-Code Generation is a stage in the OpenVADL QEMU generation pipeline, following Lowered VIAM and producing a QEMU frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[2] QEMU uses dynamic binary translation and an architecture-agnostic IR called TCG. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[3] The generated RISC-V 64 ADDI C translation function is named trans_addi and emits TCG operations including tcg_gen_add_i64 and tcg_gen_mov_i64. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[4] Lowered VIAM for RISC-V 64 ADDI represents the instruction using TCG-oriented elements such as register variables, constants, temporaries, tcg_add, and tcg_mov. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[5] The OpenVADL presentation concludes that QEMU frontends can be generated automatically from VADL specifications by lowering VIAM to TCG operations and reports up to 44% lower runtime than upstream for the generated frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL