Decoder Generation
ConceptDecoder Generation is a stage in the OpenVADL QEMU simulator generation flow. In the provided evidence, it appears as part of QEMU generation alongside VDT and the VIAM-to-TCG lowering path that ultimately emits QEMU frontend C code.
First seen 5/29/2026
Last seen 5/29/2026
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Decoder Generation
Decoder Generation is a named stage in the OpenVADL flow for generating a QEMU-based instruction-set simulator from a processor description. In the presented QEMU generation diagram, Decoder Generation appears alongside VDT and the VIAM-to-TCG transformation path as part of the generated QEMU system/frontend. [C1]
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1 connectionsOpenVADL's QEMU generation pipeline includes a decoder generation step.
CITATIONS
6 sources6 citations — click to expand
[1] Decoder Generation is shown as a stage in the QEMU generation flow alongside VDT and the generated QEMU system/frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[2] OpenVADL starts from VADL processor specifications that can include registers, instruction formats, instruction semantics, and instruction encodings, and the overview shows generation toward a QEMU simulator. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[3] QEMU is described as an open-source machine emulator using dynamic binary translation, a modular architecture, and the architecture-agnostic TCG IR. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[4] The QEMU generation flow lowers VIAM through TCG transformation and lowered VIAM before C-code generation for the QEMU frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[5] The generated C-code example for RISC-V 64 ADDI emits a QEMU TCG translation function named trans_addi using register access, an immediate constant, tcg_gen_add_i64, and tcg_gen_mov_i64. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[6] The slide deck concludes that OpenVADL enables automatic generation of QEMU frontends from VADL specifications by lowering VIAM to TCG operations, reports up to 44% lower runtime than upstream, and lists future work including vector, user-mode, floating-point, and cycle-approximate simulator support. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL