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Decoder Generation

Concept WIKI v1 · 5/29/2026

Decoder Generation is a stage in the OpenVADL QEMU simulator generation flow. In the provided evidence, it appears as part of QEMU generation alongside VDT and the VIAM-to-TCG lowering path that ultimately emits QEMU frontend C code.

Decoder Generation

Decoder Generation is a named stage in the OpenVADL flow for generating a QEMU-based instruction-set simulator from a processor description. In the presented QEMU generation diagram, Decoder Generation appears alongside VDT and the VIAM-to-TCG transformation path as part of the generated QEMU system/frontend. [C1]

Context

OpenVADL starts from a VADL specification of an instruction-set architecture. The example in the evidence shows an RV64I-style specification declaring registers, an instruction format, an ADDI instruction semantics expression, and an encoding ADDI clause. The OpenVADL overview shows this specification flowing through a frontend and VIAM architecture synthesis toward generated tools, including a QEMU simulator. [C2]

QEMU is a relevant backend because it is described as an open-source machine emulator that uses dynamic binary translation and an architecture-agnostic intermediate representation called TCG. The slides also note that QEMU's modular architecture simplifies support for new architectures and provides reusable infrastructure such as a GDB stub. [C3]

Place in the QEMU generation pipeline

The evidence separates decoder generation from semantic lowering and code emission:

  1. Decoder Generation / VDT appears at the QEMU generation level and feeds into the QEMU system. [C1]
  2. VIAM transformation lowers the architecture model toward TCG-oriented operations. [C4]
  3. Lowered VIAM and C-code generation produce QEMU frontend translation code. For the ADDI example, the generated trans_addi function obtains register operands, creates a constant immediate, emits tcg_gen_add_i64, moves the result to the destination register, and returns success. [C5]

In this flow, Decoder Generation is therefore the decoding-side component of the generated QEMU frontend, while the VIAM-to-TCG path provides the instruction behavior that is emitted as QEMU translation code. [C1]

Reported status

The slide deck concludes that OpenVADL can automatically generate QEMU frontends from VADL specifications by lowering VIAM to TCG operations. The reported evaluation claims that the generated frontend achieved up to 44% lower runtime than upstream in the presented benchmarks. Future work listed in the evidence includes TCG vector support for tensor instructions, user-mode simulation, floating-point instruction support, and a cycle-approximate simulator based on the ISS. [C6]

LINKED ENTITIES

2 links
OpenVADL USES
QEMU SUPPORTS_GENERATION_FOR

CITATIONS

6 sources
6 citations
[1] Decoder Generation is shown as a stage in the QEMU generation flow alongside VDT and the generated QEMU system/frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[2] OpenVADL starts from VADL processor specifications that can include registers, instruction formats, instruction semantics, and instruction encodings, and the overview shows generation toward a QEMU simulator. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[3] QEMU is described as an open-source machine emulator using dynamic binary translation, a modular architecture, and the architecture-agnostic TCG IR. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[4] The QEMU generation flow lowers VIAM through TCG transformation and lowered VIAM before C-code generation for the QEMU frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[5] The generated C-code example for RISC-V 64 ADDI emits a QEMU TCG translation function named trans_addi using register access, an immediate constant, tcg_gen_add_i64, and tcg_gen_mov_i64. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[6] The slide deck concludes that OpenVADL enables automatic generation of QEMU frontends from VADL specifications by lowering VIAM to TCG operations, reports up to 44% lower runtime than upstream, and lists future work including vector, user-mode, floating-point, and cycle-approximate simulator support. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL