Overview
OpenVADL is presented as a toolchain around the Vienna Architecture Description Language (VADL). A VADL specification is processed by a frontend and architecture-synthesis stage into the VADL Intermediate Architecture Model (VIAM), with generated outputs shown for an assembler/linker, compiler, QEMU simulator, hardware, and a cycle-approximate simulator. [OpenVADL overview]
The 2025 presentation Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL states that OpenVADL enables automatic generation of QEMU frontends from VADL specifications. [Automatic QEMU frontend generation]
QEMU frontend generation flow
For QEMU-based instruction-set simulation, the documented OpenVADL generation pipeline is:
- Decoder generation from the architecture model.
- TCG transformation of VIAM.
- Lowering into a lowered VIAM form expressed in TCG-like operations.
- C-code generation for a QEMU frontend.
The generated QEMU frontend executes guest programs using QEMU’s dynamic binary translation infrastructure and its architecture-agnostic Tiny Code Generator (TCG) intermediate representation. [QEMU generation pipeline]
VIAM and lowering
VIAM represents instruction semantics as an intermediate architecture model. The slides illustrate RISC-V 64 ADDI as a VIAM graph over fields such as rs1, rd, and immS, register reads and writes to X, and an add operation implementing X(rd) := X(rs1) + immS. [VIAM ADDI representation]
OpenVADL’s QEMU generation lowers this representation to TCG operations. In the RISC-V 64 ADDI example, the lowered VIAM includes register variables, a constant, a temporary, tcg_add, and tcg_mov, which are then emitted as C code using QEMU TCG helper calls such as tcg_gen_add_i64 and tcg_gen_mov_i64. [Lowered VIAM and generated C]
Evaluation and status
The cited evaluation reports Embench results for generated QEMU frontends on RISC-V 64 IM and AArch64. The conclusion states that the generated frontend achieved up to 44% lower runtime than upstream QEMU in the evaluated setting. [Evaluation results]
Future work listed in the presentation includes TCG vector support for tensor instructions, user-mode simulation, floating-point instruction support, and a cycle-approximate simulator based on the instruction-set simulator. [Future work]