VADL Intermediate Architecture Model (VIAM)

Concept

The VADL Intermediate Architecture Model (VIAM) is the intermediate representation used in the OpenVADL tool flow after processing a VADL specification. In the QEMU-generation flow, VIAM represents instruction semantics such as register reads, field accesses, arithmetic, and writes, and is lowered to TCG-oriented operations before C code is generated for a QEMU frontend.

First seen 5/29/2026

Last seen 5/29/2026

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Overview

The VADL Intermediate Architecture Model (VIAM) is the intermediate architecture representation shown in the OpenVADL tool flow between the VADL frontend and architecture synthesis. In the presented OpenVADL overview, a VADL specification is processed by a frontend into a VIAM Architecture, which is then used by downstream generators for tools such as an assembler/linker, compiler, QEMU simulator, hardware, and a cycle-approximate simulator.[1]

Role in QEMU frontend generation

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RELATIONSHIPS

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OpenVADL ← introduces 95% 1e

OpenVADL introduces and uses the VADL Intermediate Architecture Model (VIAM) as part of its compilation pipeline.

Lowered VIAM ← derived from 95% 1e

Lowered VIAM is derived from the VIAM after applying TCG transformation.

Vienna Architecture Description Language (VADL) derived from → 90% 1e

VIAM is derived from the VADL specification through the OpenVADL frontend.

LINKED ENTITIES

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OpenVADL INTRODUCES Extracted graph relationship

Lowered VIAM DERIVED_FROM Extracted graph relationship

Vienna Architecture Description Language (VADL) DERIVED_FROM Extracted graph relationship

CITATIONS

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[1] VIAM appears in the OpenVADL tool flow between the VADL frontend and architecture synthesis, with downstream generation paths for assembler/linker, compiler, QEMU simulator, hardware, and cycle-approximate simulator. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[2] The QEMU-generation flow transforms VIAM through TCG transformation into Lowered VIAM and then generates C code for a QEMU frontend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[3] OpenVADL enables automatic generation of QEMU frontends from VADL specifications by lowering VIAM to TCG operations. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[4] The VIAM example for RISC-V 64 ADDI represents X(rd) := X(rs1) + immS using nodes such as field accesses, register read and write, add, start, and instruction end. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[5] The Lowered VIAM example for RISC-V 64 ADDI contains TCG-oriented operations including tcg_add and tcg_mov along with field and variable nodes. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[6] The generated C-code example for RISC-V 64 ADDI emits tcg_gen_add_i64 and tcg_gen_mov_i64 inside a QEMU translation function. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL