Overview
The VADL Intermediate Architecture Model (VIAM) is the intermediate architecture representation shown in the OpenVADL tool flow between the VADL frontend and architecture synthesis. In the presented OpenVADL overview, a VADL specification is processed by a frontend into a VIAM Architecture, which is then used by downstream generators for tools such as an assembler/linker, compiler, QEMU simulator, hardware, and a cycle-approximate simulator.[1]
Role in QEMU frontend generation
In the QEMU-generation pipeline, VIAM is the starting intermediate representation for transforming instruction behavior into QEMU's Tiny Code Generator (TCG) form. The shown flow performs a TCG Transformation from VIAM to Lowered VIAM, followed by C-code generation that produces a QEMU frontend. The same slide also shows decoder generation feeding into the QEMU system.[2]
The presentation's conclusion summarizes this process as automatic generation of QEMU frontends from VADL specifications, achieved by lowering VIAM to TCG operations.[3]
Instruction-semantics representation
The slide deck illustrates VIAM with the RISC-V 64 ADDI instruction:
X(rd) := X(rs1) + immS
For this instruction, VIAM is depicted as a graph-like representation containing instruction-field nodes such as field<rs1> and field<rd>, a fieldAccess<immS> node, a register read read<X>, an add operation, and a register write write<X>, connected between instruction start and end markers.[4]
Lowered VIAM
The corresponding Lowered VIAM representation for the same ADDI example replaces the higher-level VIAM operations with TCG-oriented operations and variables. The depicted lowered form includes field nodes for rs1, immS, and rd, variable nodes such as register, constant, temporary, and destination variables, and TCG operations including tcg_add and tcg_mov before instr_end.[5]
Generated code example
The generated C-code example for RISC-V 64 ADDI creates QEMU TCG values for the destination register, source register, temporary, and immediate constant, then emits tcg_gen_add_i64 followed by tcg_gen_mov_i64. This demonstrates how a VIAM instruction representation can be lowered into TCG operations and emitted as a QEMU translation function.[6]