UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
PaperFirst seen 8/13/2026
Last seen 8/13/2026
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20 connectionsThe paper uses Questa RTL simulator for RTL simulation of the RISC-V processor.
The paper describes the use of ifdef constructs for managing RISC-V configuration variants in RTL and UVM.
The paper describes the use of uvm_config_db as a third configuration option.
The paper discusses functional coverage as part of the UVM verification methodology for RISC-V.
The paper discusses the use of transactors when porting UVM to the emulator.
The paper is published in Verification Horizons, a publication of Mentor, A Siemens Business.
The paper introduces and uses the golden predictor model concept for RISC-V verification.
The paper describes and uses a configuration layer for RISC-V design and verification.
The paper uses FlexMem to improve emulation performance for RISC-V verification.
The paper uses emulation as a key technique to accelerate RISC-V verification.
The paper evaluates the Codix Berkelium RISC-V processor using the described verification methodology.
The paper describes the use of Codasip Studio for processor configuration and UVM environment generation.
The paper uses the Veloce emulator to accelerate verification of the Berkelium processor.
The paper uses a scoreboard to compare outputs from the golden predictor model and the DUT.
The paper is authored by Luboš Moravec of Codasip Ltd.
The paper is authored by John Stickley of Mentor, A Siemens Business.
The paper is authored by Shakeel Jeeawoody of Mentor, A Siemens Business.
The paper describes a methodology based on UVM for verifying RISC-V processor cores.
The paper uses random test generation, running random programs in emulation in the second phase.
The paper is authored by Marcela Zachariášová of Codasip Ltd.